Abstract: A deadlock-avoidance system for a computer. In a multi-bus, multi-processor computer, one processor may request a lock on a bus, to execute a locked cycle, thereby blocking all other processors, and other agents, from access to the bus. In addition, a conflicting agent may, in effect, lock a resource which is needed by the processor to complete the cycle for which the lock was requested. These two locks can create a deadlock situation which stalls the computer: the processor and the conflicting agent have each locked a resource needed by the other. Under the invention, when a locked cycle is requested by a processor, all other operations are suspended in the computer. Then queues standing in memory controllers are emptied. If a process requested by an agent occupies a resource, such as a bridge, required by the requested locked cycle, that resource is freed. Then the locked cycle is executed.

Abstract: A system for booting a multi-processor computer. If a normal boot attempt fails, different processors are selected, one-at-a-time, for performing the boot routine. During the boot routing, all other processors are held inactive. After boot, processors are tested for health. Non-healthy processors are held inactive, and healthy processors are activated as usual.

Abstract: A method of transferring data words that include data bytes within a computer having a main memory, a processor and a cache memory, with the processor being able to cause data words to be transferred in a burst mode from the cache memory to the main memory in one of a plurality of predetermined sequences, includes the following steps: (1) determining which data words of a group of data words located in the cache memory include data bytes which have been modified, (2) selecting one sequence of data words of the plurality of predetermined sequences of data words which includes (a) all of the data words of the group of data words that include data bytes which have been modified, and (b) a minimum number of data words of the group of data words that include no data bytes which have been modified, and (3) causing the one sequence of data words selected in the selecting step to be transferred in the burst mode from the cache memory to the main memory.