Abstract: A card structure has an internal three dimensional array of implanted semiconductor chips. The card structure includes a power core and a plurality of chip cores. Each chip core is joined to the power core on opposite surfaces of the power core, and each chip core includes a compensator core having a two dimensional array of chip wells. Each chip well allows for a respective one of the semiconductor chips to be implanted therein. Further, a compliant dielectric material is disposed on the major surfaces of the compensator core except at the bottoms of the chip wells. The compliant dielectric material has a low dielectric constant and has a thermal coefficient of expansion compatible with those of the semiconductor chips and the compensator core, so that thermal expansion stability with the chips and the compensator core is maintained.

Abstract: Process for producing a card structure having an internal three-dimensional array of semiconductor chips includes providing a thermal conductor plane, applying a first compliant dielectric material on major surfaces of the thermal conductor plane, forming a two-dimensional array of chip wells in the dielectric material on each side of the thermal conductor plane, positioning and securing semiconductor chips in the chip wells, laminating a lead frame mounted on a carrier sheet over the first compliant dielectric material and the semiconductor chips, forming an electrical connection between each of the semiconductor chips and the lead frame, encapsulating the electrical connections with a filler, laminating an insulating layer and a wiring plane over the encapsulated connections, electrically connecting the lead frame and the wiring plane so as to form a chip core, and electrically connecting a power core to the chip core.

Abstract: A memory card structure is disclosed containing an embedded three dimensional array of semiconductor memory chips. The card structure includes at least one memory core and at least one power core which are joined together in an overlapping relationship. Each memory core comprises a copper-invar-copper thermal conductor plane having a two dimensional array of chip well locations on each side of the plane. Polytetrafluoroethylene covers the major surfaces of the thermal conductor plane except at the bottoms of the chip wells. Memory chips are placed in the chip wells and are covered by insulating and wiring levels. Each power core comprises at least one copper-invar-copper electrical conductor plane and polytetrafluoroethylene covering the major surfaces of the electrical conductor plane.Provision is made for providing electrical connection pathways and cooling pathways along vertical as well as horizontal planes internal to the card structure.