Patents by Inventor Bohumil Polata

Bohumil Polata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4018627
    Abstract: Defect formations and unwanted in diffusions caused by residual impurity products is prevented in a semiconductor fabrication method which includes the step of forming a composite mask which simultaneously defines base, collector and diffusion isolation openings. After these openings are defined a thin protective layer of silicon dioxide is grown over the exposed area and remains there throughout the remainder of the doping process which includes the steps of selectively covering areas which are not to be doped with photoresist and thereafter ashering the photoresist to remove it in preparation for the next ion implantation step. The thin protective layer of silicon dioxide protects nonselected areas against residual impurity products formed during removal of the photoresist.
    Type: Grant
    Filed: September 22, 1975
    Date of Patent: April 19, 1977
    Assignee: Signetics Corporation
    Inventor: Bohumil Polata
  • Patent number: 4003076
    Abstract: Single bipolar transistor memory cell in which information is stored on the collector to substrate capacitance. This capacitance may be enhanced by an additional diffused region. Storage and retrieval of information is accomplished through only two leads connected to the transistor which is operated so that a portion of the base is fully depleted during a portion of the operating memory cycle of the memory cell.
    Type: Grant
    Filed: May 5, 1975
    Date of Patent: January 11, 1977
    Assignee: Signetics Corporation
    Inventors: Bohumil Polata, James A. Marley, Jr.
  • Patent number: 3976512
    Abstract: The buried layer of an integrated circuit is produced by use of a grated mask. The growth of silicon dioxide in the exposed areas of the grate forms a stepped surface. Thereafter ion implantation in these areas and then merging the implanted regions forms a single buried region having a corrugated surface on which an epitaxial layer is grown. Such corrugated surface reduces the defect regions in the epitaxial layer.
    Type: Grant
    Filed: September 22, 1975
    Date of Patent: August 24, 1976
    Assignee: Signetics Corporation
    Inventors: Vittorio De Nora, Bohumil Polata
  • Patent number: 3940783
    Abstract: A majority charge carrier semiconductor structure including a relatively heavily doped n type support layer, a second n type layer formed on the support layer and having a relatively light doping, a p layer formed on the second n layer, and a third n type layer having a relatively heavy doping formed atop the p layer. When voltage means is applied between top and support layers principal current flow is by majority charge carriers in either direction determined by the polarity of a pre-determined voltage. Current flow occurs substantially below the critical electric field, and free of avalanche multiplication or tunneling. In alternate embodiments the doping impurity concentration may be varied to alternately provide a device wherein the magnitude of voltage reference which determines current flow in one direction or in the opposite direction may be symmetrical, asymmetrical or highly asymmetrical.
    Type: Grant
    Filed: February 11, 1974
    Date of Patent: February 24, 1976
    Assignee: Signetics Corporation
    Inventor: Bohumil Polata