Abstract: A communication system, comprising a first node, a second node, a serial communication link between the first node and the second node, configured to transmit digital video data from the first node to the second node over one or more video channels of the link. The communication system further including a hybrid link between the first node and the second node, wherein the first node and the second node are configured to transmit at least one stream of data to the other through a hybrid channel over the hybrid link. In the communication system, the bandwidth of the serial communication link is scaled according to a video pixel frequency. Further, the initial locking of the serial communication link is aided by clock information delivered over the hybrid link.

Abstract: A communication system, comprising a first node, a second node, a serial communication link between the first node and the second node, configured to transmit digital video data from the first node to the second node over one or more video channels of the link. The communication system further including a hybrid link between the first node and the second node, wherein the first node and the second node are configured to transmit at least one stream of data to the other through a hybrid channel over the hybrid link. In the communication system, the bandwidth of the serial communication link is scaled according to a video pixel frequency. Further, the initial locking of the serial communication link is aided by clock information delivered over the hybrid link.

Abstract: Provided is a method of fabricating an organic light emitting device that may form a light scattering layer having an irregular random structure at a low temperature. The method includes providing a substrate coated with a precursor layer; sequentially forming a metal layer and an organic layer on the precursor layer; performing a heat treatment of the organic layer to form an organic mask from the organic layer; patterning the metal layer by using the organic mask to form a metal mask; patterning the precursor layer by using the metal mask to form a light scattering layer having an irregular random structure; removing the metal mask and the organic mask; and sequentially stacking a planarization layer, a first electrode, an organic light emitting layer, a second electrode, and a passivation layer on the light scattering layer.

Abstract: Disclosed are organic light emitting devices and methods of fabricating the same. The organic light emitting device may include light scattering parts having irregular island-shapes irregularly arranged. The organic light emitting device may further include a planarization layer, a first electrode, an organic light emitting layer, a second electrode, and an encapsulation layer. The light scattering parts may be formed using an organic solution having a low refractive index to improve light extraction efficiency of the organic light emitting device. Additionally, the light scattering parts of the irregular island-shapes may improve the light extraction efficiency of lights of all wavelengths, so as to be applied to an organic white light emitting device. The light scattering parts of the irregular island-shapes may be formed using the organic solution by a dewetting phenomenon. The light scattering parts may be formed at a temperature of about 250 degrees Celsius or less.

Abstract: An automatic moving apparatus may include a collision prediction sensor, a control unit comparing a value measured by the collision prediction sensor, with a reference value stored in the control unit, and outputting a control signal when it may be determined that the value measured by the collision prediction sensor is higher than the reference value, and a headrest moving unit moving a headrest unit toward a passenger's head before the headrest unit comes into contact with the passenger's head, and including a stay rod connected to the headrest unit, both sides of the stay rod being placed in a vertical direction, tilting device tilting the stay rod forwards or backwards relative to a seatback in response to the control signal of the control unit, and vertical moving device moving the stay rod in a vertical direction in response to the control signal of the control unit.

Abstract: A suspension assembly of a vehicle seat may include a lumbar plate disposed within an edge of a seat back frame, and an elastic wire section connecting the edge of the seat back frame with a side of the lumbar plate, wherein the elastic wire section includes a first elastic wire, opposite ends of which may be connected to one edge of the seat back frame and at least a portion thereof may be supported by one side of the lumbar plate, and a second elastic wire, opposite ends of which may be connected to the other edge of the seat back frame and at least a portion thereof may be supported by the other side of the lumbar plate.

Abstract: An automatic moving apparatus may include a collision prediction sensor, a control unit comparing a value measured by the collision prediction sensor, with a reference value stored in the control unit, and outputting a control signal when it may be determined that the value measured by the collision prediction sensor is higher than the reference value, and a headrest moving unit moving a headrest unit toward a passenger's head before the headrest unit comes into contact with the passenger's head, and including a stay rod connected to the headrest unit, both sides of the stay rod being placed in a vertical direction, tilting device tilting the stay rod forwards or backwards relative to a seatback in response to the control signal of the control unit, and vertical moving device moving the stay rod in a vertical direction in response to the control signal of the control unit.

Abstract: A digital video interface system and method for communicating digital video data from a source device to a sink device is provided, where the clock channel is used to transmit data as well as clock signals in a bi-directional, half-duplex manner using time division multiplexing. The digital video interface system comprises one or more data channels configured to transmit digital video data from the source device to the sink device in time divisional multiplexing including a plurality of first time slots and second time slots, and a clock channel configured to transmit a clock signal from the source device to the sink device in the first time slots and configured to transmit additional data from the source device to the sink device or from the sink device to the source device in the second time slots.

Abstract: An adaptive equalizer system for use in a serial communication link uses timing information generated by a phase detector of a clock and data recovery circuit of the serial communication link and a frequency pattern of the recovered data to determine whether the data received over the serial communication link is over-equalized or under-equalized. The equalizer strength of the adaptive equalizer system is adjusted based on such determination.

Abstract: A battery powered computing device has a channel configured as a single direct current balanced differential channel. A signal transmitter is connected to the channel. The signal transmitter is configured to apply clock edge modulated signals to the channel, where the clock edge modulated signals include direct current balancing control signals. A signal receiver is connected to the channel. The signal receiver is configured to recover the direct current balancing control signals.

Abstract: A communication system, comprising a first node, a second node, a serial communication link between the first node and the second node, configured to transmit digital video data from the first node to the second node over one or more video channels of the link. The communication system further including a hybrid link between the first node and the second node, wherein the first node and the second node are configured to transmit at least one stream of data to the other through a hybrid channel over the hybrid link. In the communication system, the bandwidth of the serial communication link is scaled according to a video pixel frequency. Further, the initial locking of the serial communication link is aided by clock information delivered over the hybrid link.

Abstract: An adaptive equalizer system for use in a serial communication link uses timing information generated by a phase detector of a clock and data recovery circuit of the serial communication link and a frequency pattern of the recovered data to determine whether the data received over the serial communication link is over-equalized or under-equalized. The equalizer strength of the adaptive equalizer system is adjusted based on such determination.

Abstract: A digital video interface system and method for communicating digital video data from a source device to a sink device is provided, where the clock channel is used to transmit data as well as clock signals in a bi-directional, half-duplex manner using time division multiplexing. The digital video interface system comprises one or more data channels configured to transmit digital video data from the source device to the sink device in time divisional multiplexing including a plurality of first time slots and second time slots, and a clock channel configured to transmit a clock signal from the source device to the sink device in the first time slots and configured to transmit additional data from the source device to the sink device or from the sink device to the source device in the second time slots.

Abstract: A method and apparatus for 2× oversampling of data having jitter. In some embodiments, the invention is a clock and data recovery device including an alternating edge sampling binary phase detector, and which is configured to stabilize loop characteristics in various jitter environments and can be implemented with small hardware overhead. A transceiver that embodies the invention can be implemented as a CMOS integrated circuit using a 0.18 ?m CMOS process, with the transceiver chip being capable of recovering data having a data rate of up to 11.5 Gbps from a signal received over a serial link, while consuming no more than 540 mW from 1.8V supply, and with a bit error rate of less than 10?12.

Abstract: A battery powered computing device has a channel configured as a single direct current balanced differential channel. A signal transmitter is connected to the channel. The signal transmitter is configured to apply clock edge modulated signals to the channel, where the clock edge modulated signals include direct current balancing control signals. A signal receiver is connected to the channel. The signal receiver is configured to recover the direct current balancing control signals.

Abstract: A phase lock loop (PLL) for controlling a sampling clock or other clock, and a data sampling circuit, transceiver, or other device including such a PLL. The PLL includes a multi-range VCO, at least one fine control loop for controlling the VCO, and a coarse control loop for controlling the VCO by changing its frequency-voltage characteristic. The coarse control loop includes a frequency lock detector and voltage range monitoring logic. Typically, the frequency lock detector locks operation of the coarse control loop when the difference between the VCO output clock frequency and a reference frequency decreases to within a predetermined threshold, and the unlocked coarse control loop employs the voltage range monitoring logic to change the VCO frequency-voltage characteristic when the VCO's fine control voltage leaves a predetermined range.