Abstract: A driving unit for an STN-LCD receives input image data and generates column signal functions for selected row lines according to on/off states of pixels, and row signal functions for the selected row lines according to negative/positive states of row signals. The driving unit determines a dot product value of the column signal function and the row signal function to find a mismatch value between the column signal function and the row signal function, and determines the total number of mismatch values corresponding to the row and column signals to be applied sequentially to the liquid crystal panel. The driving unit generates column signal voltages in a first driving time period T1 determined according to the total number of mismatch values, and applies the column signal voltages in period T1 to the column lines when the row signals are applied respectively to four row lines during the period T1.

Abstract: A driving unit for an STN-LCD receives input image data and generates column signal functions for selected row lines according to on/off states of pixels, and row signal functions for the selected row lines according to negative/positive states of row signals. The driving unit determines a dot product value of the column signal function and the row signal function to find a mismatch value between the column signal function and the row signal function, and determines the total number of mismatch values corresponding to the row and column signals to be applied sequentially to the liquid crystal panel. The driving unit generates column signal voltages in a first driving time period T1 determined according to the total number of mismatch values, and applies the column signal voltages in period T1 to the column lines when the row signals are applied respectively to four row lines during the period T1.

Abstract: A voltage converter is provided. A first cell having a first port, a first node to which a second clock is input, and a first capacitor connected between the first port and the first node, transmits an input signal to the first port in response to a first clock. A second cell having a second port, a second node to which an inverse second clock is input, and a second capacitor connected between the second port and the second node, transmits a signal of the first port to the second port in response to an inverse first clock. A third cell having a final port and a third capacitor coupled between the final port and ground, transmits a signal of the second port to the final port in response to the first clock. The first node and the second node are short-circuited in response to a control signal.

Abstract: A zigzag scanning address generator includes a row address generator for generating a row address signal which stops, increases or decreases a present state in response to an enabling signal, and a column address generator for generating a column address signal which stops, increases or decreases a present state in response to the enabling signal. Therefore, the zigzag scanning address generator can generate zigzag scanning addresses according to a zigzag scanning method, simplifying the circuit configuration needed for generating the address signals corresponding to the zigzag scanning pattern.