Abstract: A computing system and a memory device are provided. The memory device includes a first memory having a first storage capacity. A second memory is also provided having a second storage capacity greater than the first storage capacity. The memory device also includes a controller to provide an external host with an address space corresponding to a third storage capacity, the third storage capacity being less than a sum of the first storage capacity and second storage capacity. The controller transmits the requested data to the external host from the first memory where data requested from the external host is stored in the first memory, and where the requested data is not stored in the first memory, transmits the requested data to the external host from the second memory.

Abstract: A computing system and a memory device are provided. The memory device includes a first memory having a first storage capacity, a second memory having a second storage capacity greater than the first storage capacity, and a controller to provide an external host with an address space corresponding to a third storage capacity, the third storage capacity being less than a sum of the first storage capacity and second storage capacity, wherein the controller, where data requested from the external host is stored in the first memory, transmits the requested data to the external host from the first memory, and where the requested data is not stored in the first memory, transmits the requested data to the external host from the second memory.

Abstract: A data recovery circuit and a method thereof, which are capable of reducing locking time and jitter, are provided. The data recovery circuit includes a frequency-locked loop, a locking detector, a delay-locked loop, and a data determination circuit. The frequency-locked loop locks the frequency of an internal clock signal fed back thereto in response to an input signal with the frequency of the input signal and generates a frequency locking signal representing that the input signal is frequency-locked with the internal clock signal. The locking detector determines whether the frequency of the internal clock signal is in a predetermined frequency range of the input signal in response to the frequency locking signal and generates a phase control signal. The delay-locked loop is controlled by the phase control signal, locks the phase of the internal clock signal with the phase of the input signal, and generates a recovery locking signal.

Abstract: A data recovery circuit and a method thereof, which are capable of reducing locking time and jitter, are provided. The data recovery circuit includes a frequency-locked loop, a locking detector, a delay-locked loop, and a data determination circuit. The frequency-locked loop locks the frequency of an internal clock signal fed back thereto in response to an input signal with the frequency of the input signal and generates a frequency locking signal representing that the input signal is frequency-locked with the internal clock signal. The locking detector determines whether the frequency of the internal clock signal is in a predetermined frequency range of the input signal in response to the frequency locking signal and generates a phase control signal. The delay-locked loop is controlled by the phase control signal, locks the phase of the internal clock signal with the phase of the input signal, and generates a recovery locking signal.