Patents by Inventor Bonnie I. Wang
Bonnie I. Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6806733Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.Type: GrantFiled: January 2, 2002Date of Patent: October 19, 2004Assignee: Altera CorporationInventors: Philip Pan, Chiakang Sung, Joseph Huang, Yan Chong, Bonnie I. Wang
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Patent number: 6798237Abstract: Integrated circuits with on-chip impedance matching techniques, which greatly reduce the number of off-chip resistors that are coupled to the integrated circuit, are provided. On-chip impedance matching circuits of the present invention are associated with each of a plurality of I/O pins on an integrated circuit. Circuitry of the present invention may include a resistor divider that has a resistor and an on-chip transistor. The resistance of the on-chip transistor and a voltage output signal of the resistor divider vary with process, temperature, and voltage of the integrated circuit. The effective channel W/L ratio of the impedance matching circuit changes in response to the voltage output signal of the resistor divider, so that changes in the impedance of the impedance matching circuit caused by the variations in process, temperature, and voltage are minimized.Type: GrantFiled: January 11, 2002Date of Patent: September 28, 2004Assignee: Altera CorporationInventors: Xiaobao Wang, Chiakang Sung, Bonnie I. Wang, Khai Nguyen
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Patent number: 6714050Abstract: Circuitry is provided to individually configure each I/O of an integrated circuit to be compatible with a different LVTTL I/O standards. This can be done with only one I/O supply voltage, where that voltage is the highest of the I/O voltages needed in a particular application. The circuitry operates by regulating the output voltage of the I/O cell so that it is above the VOH and below the maximum VIH for the LVTTL standard for which it will comply with. Since each I/O cell is individually configurable, any I/O can drive out to any LVTTL specification.Type: GrantFiled: July 3, 2001Date of Patent: March 30, 2004Assignee: Altera CorporationInventors: Cameron McClintock, Richard G. Cliff, Bonnie I. Wang
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Patent number: 6667641Abstract: A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.Type: GrantFiled: January 23, 2002Date of Patent: December 23, 2003Assignee: Altera CorporationInventors: Bonnie I. Wang, Joseph Huang, Chiakang Sung, Xiaobao Wang, In Whan Kim, Wayne Yeung, Khai Nguyen
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Patent number: 6646467Abstract: A programmable logic integrated circuit device has several features which help it perform according to the PCI Special Interest Group's Peripheral Component Interface (“PCI”) signaling protocol. Some of the registers on the device are closely coupled for data input and output to data signal input/output pins of the device. The clock signal input terminals of at least these registers are also closely coupled to the clock signal input pin of the device. Programmable input delay is provided between the data signal input/output pins and the data input terminals of the above-mentioned registers to help compensate for clock signal skew on the device.Type: GrantFiled: May 17, 2002Date of Patent: November 11, 2003Assignee: Altera CorporationInventors: Richard G. Cliff, Francis B. Heile, Joseph Huang, David W. Mendel, Bruce B. Pendersen, Chiakang Sung, Kerry Veenstra, Bonnie I. Wang
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Patent number: 6642758Abstract: A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit. In an implementation, the programmable phase shift circuitry is implemented using two programmable counters.Type: GrantFiled: December 5, 2000Date of Patent: November 4, 2003Assignee: Altera CorporationInventors: Bonnie I. Wang, Joseph Huang, Chiakang Sung, Xiaobao Wang, In Whan Kim, Wayne Yeung, Khai Nguyen
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Patent number: 6617884Abstract: A phase frequency detector (PFD) circuit (516) compares two clock signals and generates a number of outputs to indicate a phase difference between these two clock signals (513, 519). The phase frequency detector has more than three states. The PFD circuit may be used in phase locked loop (PLL) or delay locked loop (DLL) circuit in order to maintain or lock a phase relationship between the two clock signals. The PFD circuitry will allow for a fast lock acquisition time, even when there is a relatively wide frequency range between the two clock signals.Type: GrantFiled: May 28, 2002Date of Patent: September 9, 2003Assignee: Altera CorporationInventors: Xiaobao Wang, Chiakang Sung, Joseph Huang, Bonnie I. Wang, Khai Nguyen, Wayne Yeung, In Whan Kim
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Patent number: 6603329Abstract: Techniques for on-chip impedance termination are provided that substantially reduce the number of external resistors that are need to provide impedance termination at a plurality of pairs of differential input/output (I/O) pins. On-chip impedance termination circuits of the present invention may include an amplifier, a feedback loop, and an impedance termination circuit. A reference voltage is provided to a first input terminal of the amplifier. A feedback loop is coupled between an output terminal of the amplifier and a second input terminal of the amplifier. The amplifier drives its output voltage so that the voltage at the second input terminal matches the voltage at the first input terminal. The output voltage of the amplifier determines the resistance of the impedance termination circuit. The impedance termination circuit is coupled between differential I/O pins.Type: GrantFiled: January 11, 2002Date of Patent: August 5, 2003Assignee: Altera CorporationInventors: Xiaobao Wang, Chiakang Sung, Bonnie I. Wang, Khai Nguyen
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Patent number: 6535031Abstract: A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.Type: GrantFiled: May 13, 2002Date of Patent: March 18, 2003Assignee: Altera CorporationInventors: Khai Nguyen, Xiaobao Wang, In Whan Kim, Chiakang Sung, Richard G Cliff, Joseph Huang, Bonnie I Wang, Wayne Yeung
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Publication number: 20030042941Abstract: Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.Type: ApplicationFiled: August 26, 2002Publication date: March 6, 2003Applicant: Altera CorporationInventors: Bonnie I. Wang, Chiakang Sung, Joseph Huang, Khai Nguyen, Philip Pan
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Patent number: 6483886Abstract: A phase-locked loop circuit (“PLL”) is adjustable in both phase and frequency. By providing a plurality of taps on the voltage-controlled oscillator of the PLL, and providing separate multiplexers, each of which can select a different tap—one for the PLL feedback loop and one for the PLL output—one allows the user to adjust the phase of the output relative to that of the input. Similarly, by providing loadable pre-scale (divide by N), post-scale (divide by K) and feedback-scale (divide by M) counters, one allows the user to adjust the frequency of the output to be M/(NK) times that of the input.Type: GrantFiled: August 4, 1999Date of Patent: November 19, 2002Assignee: Altera CorporationInventors: Chiakang Sung, Joseph Huang, Bonnie I. Wang, Richard G. Cliff
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Publication number: 20020158671Abstract: A phase frequency detector (PFD) circuit (516) compares two clock signals and generates a number of outputs to indicate a phase difference between these two clock signals (513, 519). The phase frequency detector has more than three states. The PFD circuit may be used in phase locked loop (PLL) or delay locked loop (DLL) circuit in order to maintain or lock a phase relationship between the two clock signals. The PFD circuitry will allow for a fast lock acquisition time, even when there is a relatively wide frequency range between the two clock signals.Type: ApplicationFiled: May 28, 2002Publication date: October 31, 2002Applicant: Altera Corporation, a Delaware CorporationInventors: Xiaobao Wang, Chiakang Sung, Joseph Huang, Bonnie I. Wang, Khai Nguyen, Wayne Yeung, In Whan Kim
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Patent number: 6448820Abstract: A phase frequency detector (PFD) circuit (516) compares two clock signals and generates a number of outputs to indicate a phase difference between these two clock signals (513, 519). The phase frequency detector has more than three states. The PFD circuit may be used in phase locked loop (PLL) or delay locked loop (DLL) circuit in order to maintain or lock a phase relationship between the two clock signals. The PFD circuitry will allow for a fast lock acquisition time, even when there is a relatively wide frequency range between the two clock signals.Type: GrantFiled: November 2, 1999Date of Patent: September 10, 2002Assignee: Altera CorporationInventors: Xiaobao Wang, Chiakang Sung, Joseph Huang, Bonnie I. Wang, Khai Nguyen, Wayne Yeung, In Whan Kim
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Patent number: 6437650Abstract: A programmable logic device is provided with phase-locked loop (“PLL”) or delay-locked loop (“DLL”) circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In this way the distributed feedback loop circuit more readily provides a substantially exact match for the distributed delay experienced by the signal propagating through the clock signal distribution network that the PLL/DLL circuitry serves.Type: GrantFiled: May 15, 2001Date of Patent: August 20, 2002Assignee: Altera CorporationInventors: Chiakang Sung, Joseph Huang, Bonnie I. Wang, Robert R. N. Bielby
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Patent number: 6433579Abstract: A programmable logic device is equipped for various differential signaling schemes by providing a differential output buffer on the device that can be configured according to the needs of the particular differential signaling schemes that may be used. The buffer includes a differential output driver, an adjustable current limiting circuit between the supply voltage and the differential output driver, and an adjustable current limiting circuit between the differential output driver and ground. By selectively adjusting the two current limiting circuits, the output impedance and current, as well as the common mode output voltage and the differential output voltage can be controlled.Type: GrantFiled: May 22, 2001Date of Patent: August 13, 2002Assignee: Altera CorporationInventors: Bonnie I. Wang, Chiakang Sung, Yan Chong, Philip Pan, Khai Nguyen, Joseph Huang, Xiaobao Wang, In Whan Kim, Gopinath Rangan
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Patent number: 6400598Abstract: A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.Type: GrantFiled: April 25, 2001Date of Patent: June 4, 2002Assignee: Altera CorporationInventors: Khai Nguyen, Xiaobao Wang, In Whan Kim, Chiakang Sung, Richard G. Cliff, Joseph Huang, Bonnie I. Wang, Wayne Yeung
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Patent number: 6384629Abstract: An improved interconnection between horizontal conductors and the input to logic elements. A signal regeneration circuit is provided in the path between the horizontal conductor and the logic element, thereby isolating and boosting the signal. This allows for faster switching operation. A path is provided allowing the selective routing of signals from the horizontal conductors to the vertical conductors, without passing through a logic element. Also, a path is provided to allow a horizontal conductors to be routed to any of a plurality of vertical conductors.Type: GrantFiled: December 15, 2000Date of Patent: May 7, 2002Assignee: Altera CorporationInventors: Joseph Huang, Chiakang Sung, Bonnie I. Wang, Khai Nguyen, Xiaobao Wang, Richard G. Cliff
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Publication number: 20020043995Abstract: A phase frequency detector (PFD) circuit (516) compares two clock signals and generates a number of outputs to indicate a phase difference between these two clock signals (513, 519). The phase frequency detector has more than three states. The PFD circuit may be used in phase locked loop (PLL) or delay locked loop (DLL) circuit in order to maintain or lock a phase relationship between the two clock signals. The PFD circuitry will allow for a fast lock acquisition time, even when there is a relatively wide frequency range between the two clock signals.Type: ApplicationFiled: November 2, 1999Publication date: April 18, 2002Inventors: XIAOBAO WANG, CHIAKANG SUNG, JOSEPH HUANG, BONNIE I. WANG, KHAI NGUYEN, WAYNE YEUNG, IN WHAN KIM
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Patent number: 6373278Abstract: An LVDS interface for a programmable logic device uses phase-locked loop (“PLL”) circuits to provide data clocks for data input and output. The PLL clocks are highly accurate and each includes a multiply-by-W counter so that a multiplied and an unmultiplied clock are available. The multiplied clock is used to clock data into or out of a shift register chain serially. The unmultiplied clock is used to load or read the registers in the shift register chain in parallel. Providing both the multiplied and unmultiplied clocks from a single PLL assures that the clocks are in proper phase relationship so that the serial inputting or outputting, and the parallel loading or unloading, are properly synchronized.Type: GrantFiled: January 11, 2001Date of Patent: April 16, 2002Assignee: Altera CorporationInventors: Chiakang Sung, Bonnie I. Wang, Richard G. Cliff
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Patent number: 6369624Abstract: A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.Type: GrantFiled: November 2, 1999Date of Patent: April 9, 2002Assignee: Altera CorporationInventors: Bonnie I. Wang, Joseph Huang, Chiakang Sung, Xiaobao Wang, In Whan Kim, Wayne Yeung, Khai Nguyen