Patents by Inventor Boo-Hyun Ham

Boo-Hyun Ham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10643888
    Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: May 5, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Su Kim, Dong-Woon Park, Tae-Hoi Park, Yong-Kug Bae, Tae-Hwan Oh, Chang-Hoon Lee, Boo-Hyun Ham
  • Patent number: 10553429
    Abstract: A method of forming a pattern of a semiconductor device includes forming a mask and a sacrificial layer on a substrate, etching the sacrificial layer in a first area of the substrate to form first units, each having a first width and a first distance from an adjacent unit, etching the sacrificial layer in a second area of the substrate to form second units, each having a second width equal to the first distance and being spaced apart from an adjacent unit by a second distance equal to the first width, forming a spacer conformally covering the first and second units, the spacer having a first thickness and being merged between the second units, removing a portion of the spacer on upper surfaces of the first and second units, and etching the mask in a region from which first and second units have been removed.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: February 4, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Boo Hyun Ham, Hyun Jae Kang, Sung Sik Park, Yong Kug Bae, Kwang Sub Yoon, Bum Joon Youn, Hyun Chang Lee
  • Patent number: 10276373
    Abstract: A method for manufacturing a semiconductor device includes forming an etch target layer on a semiconductor substrate, forming a first photoresist pattern disposed on the etch target layer, irradiating ultraviolet (UV) light in an oxygen-containing atmosphere to remove the first photoresist pattern from the etch target layer, and forming a second photoresist pattern on the etch target layer.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: April 30, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Chul Jeong, Tae Kyu Lee, Sung Sik Park, Joon Soo Park, Kwang Sub Yoon, Boo Hyun Ham
  • Publication number: 20180096840
    Abstract: A method for manufacturing a semiconductor device includes forming an etch target layer on a semiconductor substrate, forming a first photoresist pattern disposed on the etch target layer, irradiating ultraviolet (UV) light in an oxygen-containing atmosphere to remove the first photoresist pattern from the etch target layer, and forming a second photoresist pattern on the etch target layer.
    Type: Application
    Filed: April 19, 2017
    Publication date: April 5, 2018
    Inventors: Yong Chul JEONG, Tae Kyu LEE, Sung Sik PARK, Joon Soo PARK, Kwang Sub YOON, Boo Hyun HAM
  • Publication number: 20170278745
    Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.
    Type: Application
    Filed: June 13, 2017
    Publication date: September 28, 2017
    Inventors: Jong-Su Kim, Dong-Woon Park, Tae-Hoi Park, Yong-Kug Bae, Tae-Hwan Oh, Chang-Hoon Lee, Boo-Hyun Ham
  • Patent number: 9711395
    Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: July 18, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Su Kim, Dong-Woon Park, Tae-Hoi Park, Yong-Kug Bae, Tae-Hwan Oh, Chang-Hoon Lee, Boo-Hyun Ham
  • Patent number: 9704721
    Abstract: Provided are a method of forming key patterns and a method of fabricating a semiconductor device using the same. The method of forming key patterns may include forming gate and key patterns on a cell region and a scribe lane region, respectively. Here, the key patterns may be formed to have a large width and a larger pitch than those of the gate patterns.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: July 11, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunchang Lee, Boo-Hyun Ham, Yongkug Bae, Ja-Min Koo, Jonghwa Baek, Heeju Shin, Rankyung Jung
  • Publication number: 20170148643
    Abstract: A method of forming a pattern of a semiconductor device includes forming a mask and a sacrificial layer on a substrate, etching the sacrificial layer in a first area of the substrate to form first units, each having a first width and a first distance from an adjacent unit, etching the sacrificial layer in a second area of the substrate to form second units, each having a second width equal to the first distance and being spaced apart from an adjacent unit by a second distance equal to the first width, forming a spacer conformally covering the first and second units, the spacer having a first thickness and being merged between the second units, removing a portion of the spacer on upper surfaces of the first and second units, and etching the mask in a region from which first and second units have been removed.
    Type: Application
    Filed: November 18, 2016
    Publication date: May 25, 2017
    Inventors: Boo Hyun HAM, Hyun Jae KANG, Sung Sik PARK, Yong Kug BAE, Kwang Sub YOON, Bum Joon YOUN, Hyun Chang LEE
  • Publication number: 20160155662
    Abstract: Provided are a method of forming key patterns and a method of fabricating a semiconductor device using the same. The method of forming key patterns may include forming gate and key patterns on a cell region and a scribe lane region, respectively. Here, the key patterns may be formed to have a large width and a larger pitch than those of the gate patterns.
    Type: Application
    Filed: November 17, 2015
    Publication date: June 2, 2016
    Inventors: Hyunchang LEE, Boo-Hyun Ham, Yongkug Bae, Ja-Min Koo, Jonghwa Baek, Heeju Shin, Rankyung Jung
  • Publication number: 20160035617
    Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.
    Type: Application
    Filed: July 28, 2015
    Publication date: February 4, 2016
    Inventors: Jong-Su Kim, Dong-Woon Park, Tae-Hoi Park, Yong-Kug Bae, Tae-Hwan Oh, Chang-Hoon Lee, Boo-Hyun Ham