Abstract: A semiconductor wafer has different impurity concentrations in respective regions and gate patterns have different lengths in the respective regions. The semiconductor wafer has different impurity concentrations in a central region, an intermediate region, and an outer region. The gate patterns have different lengths in the central region, the intermediate region, and the outer region. Accordingly, the semiconductor wafer may have a substantially uniform threshold voltage throughout the semiconductor wafer.

Abstract: A semiconductor wafer has different impurity concentrations in respective regions and gate patterns have different lengths in the respective regions. The semiconductor wafer has different impurity concentrations in a central region, an intermediate region, and an outer region. The gate patterns have different lengths in the central region, the intermediate region, and the outer region. Accordingly, the semiconductor wafer may have a substantially uniform threshold voltage throughout the semiconductor wafer.

Abstract: A semiconductor wafer has different impurity concentrations in respective regions and gate patterns have different lengths in the respective regions. The semiconductor wafer has different impurity concentrations in a central region, an intermediate region, and an outer region. The gate patterns have different lengths in the central region, the intermediate region, and the outer region. Accordingly, the semiconductor wafer may have a substantially uniform threshold voltage throughout the semiconductor wafer.

Abstract: A first power supply node supplies a first voltage level during a normal operational mode, and a second power supply node supplies a second voltage level during the normal operational mode. An input circuit, which is connected to the first power supply node, receives an input signal and generates a corresponding signal having the first voltage level during the normal operational mode. An output circuit, which is connected to the second power supply node, receives the signal having the first voltage level and generates a corresponding output signal having the second voltage level during the normal operational mode. A detection circuit detects an interruption in the supply of the first voltage level by the first power supply node, and electrically blocks at least one leakage current path in the output circuit during the interruption.

Abstract: An input/output buffer is operative in an analog mode and a digital mode. The buffer includes a pad, a digital signal line which includes a transmission gate connected to the pad, an analog signal line connected to the pad, an analog/digital mode controller which sets an output level of the digital signal line in the analog mode, and a transmission gate controller which controls the transmission gate when a signal voltage of the pad exceeds a reference voltage.

Abstract: Disclosed is a ROM device with a repair function where defective cells are repaired by a bit cell unit. The defective cells are repaired using a ground or operating (e.g., a supply) voltage line incorporated in the ROM device. This allows the defective cells to be repaired without separate redundant cells. After repairing, a test operation for replaced cells is not needed.

Abstract: A semiconductor wafer has different impurity concentrations in respective regions and gate patterns have different lengths in the respective regions. The semiconductor wafer has different impurity concentrations in a central region, an intermediate region, and an outer region. The gate patterns have different lengths in the central region, the intermediate region, and the outer region. Accordingly, the semiconductor wafer may have a substantially uniform threshold voltage throughout the semiconductor wafer.

Abstract: A first power supply node supplies a first voltage level during a normal operational mode, and a second power supply node supplies a second voltage level during the normal operational mode. An input circuit, which is connected to the first power supply node, receives an input signal and generates a corresponding signal having the first voltage level during the normal operational mode. An output circuit, which is connected to the second power supply node, receives the signal having the first voltage level and generates a corresponding output signal having the second voltage level during the normal operational mode. A detection circuit detects an interruption in the supply of the first voltage level by the first power supply node, and electrically blocks at least one leakage current path in the output circuit during the interruption.

Abstract: An input/output buffer is operative in an analog mode and a digital mode. The buffer includes a pad, a digital signal line which includes a transmission gate connected to the pad, an analog signal line connected to the pad, an analog/digital mode controller which sets an output level of the digital signal line in the analog mode, and a transmission gate controller which controls the transmission gate when a signal voltage of the pad exceeds a reference voltage.

Abstract: Disclosed is a ROM device with a repair function where defective cells are repaired by a bit cell unit. The defective cells are repaired using a ground or operating (e.g., a supply) voltage line incorporated in the ROM device. This allows the defective cells to be repaired without separate redundant cells. After repairing, a test operation for replaced cells is not needed.

Abstract: A semiconductor device with embedded memory cells is provided, wherein the device comprises a memory block, a logic block for inputting and outputting data with the memory block and performing specific functions, and an embedded test circuit block for testing the memory block with the signals input from outside the device. The device comprises a plurality of signal terminal groups for sending and receiving signals to and from outside the device to perform a normal operation, a direct access test and a built-in self test.

Abstract: A semiconductor device having an apparatus is provided for recognizing chip identification capable of minimizing the number of pads. The apparatus for recognizing chip identification comprises a counter circuit for counting a clock signal in response to a reset signal and decoding the counted clock signal to produce at least one decoding signal; and a fuse circuit comprising a plurality of fuse arrays, each fuse of the plurality of fuse arrays representing chip identification information, for outputting an output signal indicating whether each fuse of the plurality of fuse arrays is cut in response to the at least one decoding signal. The apparatus for recognizing chip identification minimizes the number of pads required for a semiconductor chip, occupies a small portion of a semiconductor device, and reads chip information in a package state of a semiconductor device.

Abstract: A semiconductor memory device comprises a plurality of normal memory cell arrays having a first and a second data state, a plurality of redundant memory cell arrays having a first and a second data state for substituting for the normal memory cell arrays, a plurality of input/output lines, a plurality of complementary input/output lines, a plurality of first control signals for substituting a redundant memory cell array having the first data state for a defective normal memory cell array having the first data state, and a plurality of second control signals for substituting a redundant memory cell array having the second data state for a defective normal memory cell array having the second data state. In the device, a control circuit for transmitting the complementary input/output data to the plurality of input/output lines, and the input/output data to the plurality of complementary input/output data lines according to the circumstances is provided.