Abstract: The invention is a system and method for reconfigurable computers. The invention involves a plurality of reconfigurable component clusters (RCCs), each of which can change their respective configuration upon receiving a configuration command. The invention uses a reconfiguration network for distributing the configuration command to the RCCs, wherein the reconfiguration network comprises a plurality of cells, wherein each RCC is connected to a cell.

Abstract: Techniques for combining volatile and non-volatile programmable logic into one integrated circuit (IC) are provided. An IC is segregated into two portions. A first block of programmable logic is configured by bits stored in on-chip non-volatile memory. A second block of programmable logic is configured by bits stored in off-chip memory. The function of IO banks on the IC is multiplexed between the two logic blocks of the IC. The programmable logic in the first block can be configured and fully functional in a fraction of the time that the programmable logic in the second block can be configured. The programmable logic in the first block can configure fast enough and have enough independence to assist in the configuration of the second block. The non-volatile memory can also provide security features to a user design, such as encryption.

Abstract: Techniques are provided for improving signal timing characteristics of differential input/output (IO) circuits on programmable logic integrated circuits. A differential buffer receives differential signals applied to differential input pins. The output signals of the differential buffer are routed to two hard IO decoder blocks that are located in two adjacent rows/columns of programmable logic elements. Each IO decoder block has a data-in register that receives output signals of the differential buffer. The data-in registers in two adjacent IO decoder blocks support a double clocking technique. IO decoder blocks of the present invention have reduced setup times, hold times, and sampling windows relative to soft DDIO blocks, and have a minimal impact on die area.

Abstract: A description of components in a reconfigurable data center is received. A set of components from the description is selected for a physical platform based on a logical platform specification.

Abstract: A reconfigurable memory system includes processors and memory modules. A reconfiguration system is operable to reconfigure the memory system into multiple configurations. In each configuration, one or more memory modules are provisioned for each processor.

Abstract: A system installer is operable to configure hardware components in a reconfigurable data center for a hardware platform. The system installer is also operable to install software on the hardware platform.

Abstract: A service configuration for a service is generated using a service specification and at least one library including at least one of a hardware component and a software component available to be implemented for the service.

Abstract: Testing methods and systems including processing of simulation data and test patterns are described herein.

Abstract: A method of designing a custom circuit device begins with a high level architecture of subsystems coupled by virtual wires. The method comprises first through third steps. The first step comprises spatially placing the subsystems onto tiles. The second step comprises routing the virtual wires that cross boundaries of the tiles onto an interconnect architecture. The interconnect architecture comprises switches and registers. Some of the switches route a signal from a first subsystem located on a first tile to a second subsystem located on a second tile. At least two of the registers consecutively latch the signal at a time interval of no more than a repeating time period. The third step comprises scheduling of tasks according to clock cycles. According to an embodiment of the method, the repeating time period comprises a clock cycle period. According to another embodiment of the method, the repeating time period comprises a multiple of the clock cycle period.