Patents by Inventor Bor-Ray Su

Bor-Ray Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7844408
    Abstract: A time domain reflectometry (“TDR”) testing method that includes storing test data resulted from a TDR test applied on an electronic component, displaying the test data, identifying a distinctive portion of the test data corresponding to a defective location in the electronic component, modifying the distinctive portion of the test data, and computing the modified test data to verify whether a predetermined requirement is satisfied.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: November 30, 2010
    Assignee: NVIDIA Corporation
    Inventors: Ming-Kia Chen, Bor-Ray Su
  • Publication number: 20090105971
    Abstract: A TDR testing method comprises storing test data resulted from a TDR test applied on an electronic component, displaying the test data, identifying a distinctive portion of the test data corresponding to a defective location in the electronic component, modifying the distinctive portion of the test data, and computing the modified test data to verify whether a predetermined requirement is satisfied.
    Type: Application
    Filed: October 19, 2007
    Publication date: April 23, 2009
    Inventors: Ming-Kia Chen, Bor-Ray Su
  • Publication number: 20020118528
    Abstract: The invention provides a substrate layout method and structure of a ball grid array to reduce cross talk of adjacent signals. The substrate comprises a plurality of signal pads formed on a die, a ring around the die, and a plurality of signal fingers around the ring. The substrate layout method for reducing cross talk of adjacent signals is as follows: First, forming a guard pad between two adjacent signal pads. Second, forming a guard finger between two adjacent signal fingers. Next, forming a bonding wire to connect the guard pad to the ring. Then, forming another bonding wire to connect the ring to the guard finger. Subsequently, forming a guard trace to connect the guard finger to a via at the edge of the substrate, and connecting the guard trace to a short-circuiting place through the via.
    Type: Application
    Filed: March 19, 2001
    Publication date: August 29, 2002
    Inventors: Bor-Ray Su, Chin-Chih Li
  • Publication number: 20020074162
    Abstract: The invention provides a substrate layout method and structure of a ball grid array to reduce cross talk of adjacent signals. The substrate comprises a plurality of signal pads formed on a die, a ring around the die, and a plurality of signal fingers around the ring. The substrate layout method for reducing cross talk of adjacent signals is as follows: First, forming a guard pad between two adjacent signal pads. Second, forming a guard finger between two adjacent signal fingers. Next, forming a bonding wire to connect the guard pad to the ring. Then, forming another bonding wire to connect the ring to the guard finger. Subsequently, forming a guard trace to connect the guard finger to a via at the edge of the substrate, and connecting the guard trace to a short-circuiting place through the via.
    Type: Application
    Filed: June 20, 2001
    Publication date: June 20, 2002
    Inventors: Bor-Ray Su, Chin-Chih Li