Patents by Inventor Bor-Wen Chan
Bor-Wen Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9947758Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.Type: GrantFiled: October 18, 2016Date of Patent: April 17, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tan-Chen Lee, Bor-Wen Chan
-
Patent number: 9899494Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.Type: GrantFiled: September 19, 2014Date of Patent: February 20, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tan-Chen Lee, Bor-Wen Chan
-
Publication number: 20170040432Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.Type: ApplicationFiled: October 18, 2016Publication date: February 9, 2017Inventors: Tan-Chen Lee, Bor-Wen Chan
-
Publication number: 20150044844Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.Type: ApplicationFiled: September 19, 2014Publication date: February 12, 2015Inventors: Tan-Chen Lee, Bor-Wen Chan
-
Patent number: 8841192Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.Type: GrantFiled: April 11, 2012Date of Patent: September 23, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tan-Chen Lee, Bor-Wen Chan
-
Patent number: 8785313Abstract: A method of manufacturing a semiconductor device, and the method includes forming a stack of a work function layer, a blocking structure, and a metal cap layer sequentially on a substrate. The forming of the blocking structure includes sequentially depositing at least a metal diffusion prevention layer over the work function layer and an electrical performance enhancement layer over the metal diffusion prevention layer before forming the metal cap layer. The electrical performance enhancement layer includes a TiN layer having a Ti/N ratio greater than 1.Type: GrantFiled: September 23, 2013Date of Patent: July 22, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bor-Wen Chan, Hsueh Wen Tsau
-
Publication number: 20140024207Abstract: A method of manufacturing a semiconductor device, and the method includes forming a stack of a work function layer, a blocking structure, and a metal cap layer sequentially on a substrate. The forming of the blocking structure includes sequentially depositing at least a metal diffusion prevention layer over the work function layer and an electrical performance enhancement layer over the metal diffusion prevention layer before forming the metal cap layer. The electrical performance enhancement layer includes a TiN layer having a Ti/N ratio greater than 1.Type: ApplicationFiled: September 23, 2013Publication date: January 23, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Bor-Wen CHAN, Hsueh Wen TSAU
-
Patent number: 8564072Abstract: A semiconductor device includes a blocking structure between a metal layer and at least one underlying layer. The blocking structure has a first layer configured for preventing diffusion of metal from the metal layer into the at least one underlying layer, and a second layer configured for enhancing electrical performance of the semiconductor device.Type: GrantFiled: April 2, 2010Date of Patent: October 22, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bor-Wen Chan, Hsueh Wen Tsau
-
Patent number: 8513107Abstract: A structure and method for replacement metal gate technology is provided for use in conjunction with semiconductor fins or other devices. An opening is formed in a dielectric by removing a sacrificial gate material such as polysilicon. The surfaces of the semiconductor fin within which a transistor channel is formed, are exposed in the opening. A replacement metal gate is formed by forming a diffusion barrier layer within the opening and over a gate dielectric material, the diffusion barrier layer formation advantageously followed by an in-situ plasma treatment operation. The treatment operation utilizes at least one of argon and hydrogen and cures surface defects in the diffusion barrier layer enabling the diffusion barrier layer to be formed to a lesser thickness. The treatment operation decreases resistivity, densifies and alters the atomic ratio of the diffusion barrier layer, and is followed by metal deposition.Type: GrantFiled: January 26, 2010Date of Patent: August 20, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bor-Wen Chan, Fang Wen Tsai
-
Patent number: 8357603Abstract: The present disclosure provides various methods of fabricating a semiconductor device. A method of fabricating a semiconductor device includes providing a semiconductor substrate and forming a gate structure over the substrate. The gate structure includes a first spacer and a second spacer formed apart from the first spacer. The gate structure also includes a dummy gate formed between the first and second spacers. The method also includes removing a portion of the dummy gate from the gate structure thereby forming a partial trench. Additionally, the method includes removing a portion of the first spacer and a portion of the second spacer adjacent the partial trench thereby forming a widened portion of the partial trench. In addition, the method includes removing a remaining portion of the dummy gate from the gate structure thereby forming a full trench. A high k film and a metal gate are formed in the full trench.Type: GrantFiled: December 18, 2009Date of Patent: January 22, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bor-Wen Chan, Hsueh Wen Tsau, Kuang-Yuan Hsu
-
Patent number: 8299508Abstract: A semiconductor device includes a substrate having shallow trench isolation and source/drain regions located therein, a gate stack located on the substrate between the source/drain regions, a first gate spacer on the sidewall of the gate stack, and a second gate spacer on the sidewall of the first gate spacer.Type: GrantFiled: April 9, 2010Date of Patent: October 30, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bor Chiuan Hsieh, Han-Ping Chung, Chih-Hsin Ko, Bor-Wen Chan, Hun-Jan Tao
-
Publication number: 20120196420Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.Type: ApplicationFiled: April 11, 2012Publication date: August 2, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tan-Chen Lee, Bor-Wen Chan
-
Patent number: 8173540Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.Type: GrantFiled: October 14, 2010Date of Patent: May 8, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tan-Chen Lee, Bor-Wen Chan
-
Patent number: 8093117Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a substrate. A dummy gate is formed over the substrate. A dielectric material is formed around the dummy gate. The dummy gate is then removed to form an opening in the dielectric material. Thereafter, a work function metal layer is formed to partially fill the opening. The remainder of the opening is then filled with a conductive layer using one of a polysilicon substitute method and a spin coating method.Type: GrantFiled: January 14, 2010Date of Patent: January 10, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsueh Wen Tsau, Kuang-Yuan Hsu, Bor-Wen Chan
-
Publication number: 20110241130Abstract: A semiconductor device includes a blocking structure between a metal layer and at least one underlying layer. The blocking structure has a first layer configured for preventing diffusion of metal from the metal layer into the at least one underlying layer, and a second layer configured for enhancing electrical performance of the semiconductor device.Type: ApplicationFiled: April 2, 2010Publication date: October 6, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Bor-Wen CHAN, Hsueh Wen Tsau
-
Publication number: 20110183508Abstract: A structure and method for replacement metal gate technology is provided for use in conjunction with semiconductor fins or other devices. An opening is formed in a dielectric by removing a sacrificial gate material such as polysilicon. The surfaces of the semiconductor fin within which a transistor channel is formed, are exposed in the opening. A replacement metal gate is formed by forming a diffusion barrier layer within the opening and over a gate dielectric material, the diffusion barrier layer formation advantageously followed by an in-situ plasma treatment operation. The treatment operation utilizes at least one of argon and hydrogen and cures surface defects in the diffusion barrier layer enabling the diffusion barrier layer to be formed to a lesser thickness. The treatment operation decreases resistivity, densifies and alters the atomic ratio of the diffusion barrier layer, and is followed by metal deposition.Type: ApplicationFiled: January 26, 2010Publication date: July 28, 2011Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bor-Wen Chan, Fang Wen Tsai
-
Publication number: 20110171820Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a substrate. A dummy gate is formed over the substrate. A dielectric material is formed around the dummy gate. The dummy gate is then removed to form an opening in the dielectric material. Thereafter, a work function metal layer is formed to partially fill the opening. The remainder of the opening is then filled with a conductive layer using one of a polysilicon substitute method and a spin coating method.Type: ApplicationFiled: January 14, 2010Publication date: July 14, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsueh Wen Tsau, Kuang-Yuan Hsu, Bor-Wen Chan
-
Publication number: 20110151655Abstract: The present disclosure provides various methods of fabricating a semiconductor device. A method of fabricating a semiconductor device includes providing a semiconductor substrate and forming a gate structure over the substrate. The gate structure includes a first spacer and a second spacer formed apart from the first spacer. The gate structure also includes a dummy gate formed between the first and second spacers. The method also includes removing a portion of the dummy gate from the gate structure thereby forming a partial trench. Additionally, the method includes removing a portion of the first spacer and a portion of the second spacer adjacent the partial trench thereby forming a widened portion of the partial trench. In addition, the method includes removing a remaining portion of the dummy gate from the gate structure thereby forming a full trench. A high k film and a metal gate are formed in the full trench.Type: ApplicationFiled: December 18, 2009Publication date: June 23, 2011Inventors: Bor-Wen Chan, Hsueh Wen Tsau, Kuang-Yuan Hsu
-
Publication number: 20110031538Abstract: A semiconductor device includes a substrate having shallow trench isolation and source/drain regions located therein, a gate stack located on the substrate between the source/drain regions, a first gate spacer on the sidewall of the gate stack, and a second gate spacer on the sidewall of the first gate spacer.Type: ApplicationFiled: April 9, 2010Publication date: February 10, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Bor Chiuan HSIEH, Han-Ping CHUNG, Chih-Hsin KO, Bor-Wen CHAN, Hun-Jan TAO
-
Publication number: 20110027958Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.Type: ApplicationFiled: October 14, 2010Publication date: February 3, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tan-Chen Lee, Bor-Wen Chan