Abstract: A circuit and method for limiting the power supplied to a load are provided. The circuit and method prevent power supplied to the load from exceeding a power threshold for a programmable amount of time specified in a timer. The circuit includes a voltage controlled current source coupled to the load. A current multiplier divider is coupled to the voltage controlled current source and a timer is coupled to the load. A comparator with an adaptive threshold is coupled to the current multiplier divider and the input for controlling the timer to limit the power supplied to the load.

Abstract: A timer circuit includes a current mirror, a capacitor, a first switch, a resistor and a comparator. The current mirror receives a reference current and provides first and second currents with a predefined current ratio. The capacitor receives the first current as a sinking current or as a sourcing current. The first switch, controlled by a control signal, allows the capacitor to be charged by the first current or be discharged. The resistor is biased by the second current to provide an adaptive reference voltage. The comparator compares the voltage across the capacitor and the adaptive reference voltage and triggers an output signal when the capacitor voltage is increased to the adaptive reference voltage.

Abstract: A circuit and method for limiting the power supplied to a load are provided. The circuit and method prevent power supplied to the load from exceeding a power threshold for a programmable amount of time specified in a timer. The circuit includes a voltage controlled current source coupled to the load. A current multiplier divider is coupled to the voltage controlled current source and a timer is coupled to the load. A comparator with an adaptive threshold is coupled to the current multiplier divider and the input for controlling the timer to limit the power supplied to the load.

Abstract: A timer circuit includes a current mirror, a capacitor, a first switch, a resistor and a comparator. The current mirror receives a reference current and provides first and second currents with a predefined current ratio. The first switch, controlled by a control signal, allows the capacitor to be charged by the first current or be discharged. The resistor is biased by the second current to provide an adaptive reference voltage. The comparator compares the voltage across the capacitor and the adaptive reference voltage and triggers an output signal when the capacitor voltage is increased to the adaptive reference voltage. Alternately, the timer circuit includes a pin for coupling to an external resistor and an open pin detector circuit to detect the presence of the external resistor and to automatically select the adaptive reference voltage if a resistor is present or an internal reference voltage if the resistor is absent.

Abstract: A timer circuit includes a current mirror, a capacitor, a first switch, a resistor and a comparator. The current mirror receives a reference current and provides first and second currents with a predefined current ratio. The capacitor receives the first current as a sinking current or as a sourcing current. The first switch, controlled by a control signal, allows the capacitor to be charged by the first current or be discharged. The resistor is biased by the second current to provide an adaptive reference voltage. The comparator compares the voltage across the capacitor and the adaptive reference voltage and triggers an output signal when the capacitor voltage is increased to the adaptive reference voltage.

Abstract: An overcurrent protection circuit for a power transistor includes a transconductance amplifier and a bias current circuit. The transconductance amplifier receives a first signal indicative of the magnitude of the load current conducted by the power transistor and a reference voltage and provides a second signal for controlling the load current. The transconductance amplifier further provides a third signal having a first logical state indicating normal operation and a second logical state indicating an overcurrent condition at the power transistor. The bias current circuit provides an output bias current to the transconductance amplifier in response to the third signal where the output bias current has a nominal current value in normal operation and an increased current value in an overcurrent condition. In this manner, a boost current is provided to the transconductance amplifier to increase the current limit response time when an overcurrent condition is detected.

Abstract: An overcurrent protection circuit for a power transistor includes a transconductance amplifier and a bias current circuit. The transconductance amplifier receives a first signal indicative of the magnitude of the load current conducted by the power transistor and a reference voltage and provides a second signal for controlling the load current. The transconductance amplifier further provides a third signal having a first logical state indicating normal operation and a second logical state indicating an overcurrent condition at the power transistor. The bias current circuit provides an output bias current to the transconductance amplifier in response to the third signal where the output bias current has a nominal current value in normal operation and an increased current value in an overcurrent condition. In this manner, a boost current is provided to the transconductance amplifier to increase the current limit response time when an overcurrent condition is detected.

Abstract: A timer circuit includes a current mirror, a capacitor, a first switch, a resistor and a comparator. The current mirror receives a reference current and provides first and second currents with a predefined current ratio. The first switch, controlled by a control signal, allows the capacitor to be charged by the first current or be discharged. The resistor is biased by the second current to provide an adaptive reference voltage. The comparator compares the voltage across the capacitor and the adaptive reference voltage and triggers an output signal when the capacitor voltage is increased to the adaptive reference voltage. Alternately, the timer circuit includes a pin for coupling to an external resistor and an open pin detector circuit to detect the presence of the external resistor and to automatically select the adaptive reference voltage if a resistor is present or an internal reference voltage if the resistor is absent.

Abstract: A magnetic data storage and retrieval system includes a magnetoresistive head, a resistor, a preamplifier circuit, a voltage measurement circuit, and a resistance calculation circuit. The preamplifier circuit is operably coupled to the magnetoresistive head and the resistor, and applies a first current to the magnetoresistive head and a second current to the resistor. The voltage measurement circuit measures a first voltage across the magnetoresistive head and a second voltage across the resistor. The resistance calculation circuit calculates a resistance of the magnetoresistive head based upon the first and second voltages.

Abstract: A read/write system for reading information from a magnetic storage medium using a magnetoresistive head and for providing an output signal representative of the information read includes a differential pair circuit, an input voltage offset compensation circuit, and an input current offset compensation circuit. The differential pair circuit is ac coupled to first and second input signal nodes and includes first and second transistors, first and second load resistors, and a current generator. The input voltage offset compensation circuit is coupled to the differential pair circuit and includes a switch network and a Gm stage. The input current offset compensation circuit is coupled to the differential pair circuit and includes an integrator circuit and first and second biasing resistors.

Abstract: A magnetic data storage and retrieval system includes a magnetoresistive head, a resistor, a preamplifier circuit, a voltage measurement circuit, and a resistance calculation circuit. The preamplifier circuit is operably coupled to the magnetoresistive head and the resistor, and applies a first current to the magnetoresistive head and a second current to the resistor. The voltage measurement circuit measures a first voltage across the magnetoresistive head and a second voltage across the resistor. The resistance calculation circuit calculates a resistance of the magnetoresistive head based upon the first and second voltages.

Abstract: A read/write system for reading information from a magnetic storage medium using a magnetoresistive head and for providing an output signal representative of the information read includes a differential pair circuit, an input voltage offset compensation circuit, and an input current offset compensation circuit. The differential pair circuit is ac coupled to first and second input signal nodes and includes first and second transistors, first and second load resistors, and a current generator. The input voltage offset compensation circuit is coupled to the differential pair circuit and includes a switch network and a Gm stage. The input current offset compensation circuit is coupled to the differential pair circuit and includes an integrator circuit and first and second biasing resistors.

Abstract: An improved integrated self-adjustable continuous time band pass filter based upon a Gm cell with Gm compensation and bipolar transistors for use in a low power processing system for processing bursted amplitude modulated signals performing impedance-related measurements across a load. The system may be used for estimating stroke volume using the output and/or estimating hemodynamic maximum sensor rate using the output. The improved Gm cell provides for stabilization of the transconductance by compensating for manufacturing process variation of the value of the linearizing resistance RG by varying the transconductance bias current using a feedback signal proportional to the resistance of a resistor which is a replicate of the linearizing resistor.

Abstract: A low power processing system for processing bursted amplitude modulated signals performing impedance-related measurements across a load including injecting current pulses of constant amplitude across the load using at least a first electrode and a second electrode, the current pulses including bursts of a plurality of pulses at a pulse frequency at which the current pulses are repeated, the bursts transmitted at a burst frequency; detecting voltages across at least a third electrode and a fourth electrode; high pass filtering the voltages to produce filtered voltages; amplifying the filtered voltages to produce amplified voltage signals; bandpass filtering the amplified voltage signals with a bandpass filter with a center frequency equal to approximately the pulse frequency to generate first filtered signals; rectifying the first filtered signals to produce rectified signals; integrating the rectified signals to produce integrated signals; sampling-and-holding the integrated signals after each burst to captu