Patents by Inventor Boris Feigin

Boris Feigin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11947814
    Abstract: A storage system determines a change in storage system geometry that affects at least one previously formed resiliency group of storage system resources. The storage system forms at least one resiliency group of storage system resources in accordance with rules that emphasize stability of formation of resiliency groups. The storage system accesses data stripes across storage system resources of resiliency groups.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: April 2, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: Ian Juch, Haijie Xiao, Hao Liu, Boris Feigin
  • Patent number: 11886334
    Abstract: A storage system has NVRAM (non-volatile random-access memory), solid-state storage memory, and a processor to perform a method. The method includes allocating virtual units of NVRAM with mapping of the virtual units to physical memory. The method includes writing data having various sizes into allocated first virtual units of memory and into allocated second virtual units of memory. The first virtual units of memory each include a first contiguous physical addressed amount of NVRAM having a first size. The second virtual units of memory each include an amount of NVRAM having a second size. The method includes relocating at least some of the data such that a portion of the allocated second virtual units of memory become available for the allocating.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: January 30, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: Hari Kannan, Ying Gao, Boris Feigin
  • Publication number: 20230418496
    Abstract: One or more performance parameters associated with data stored at a storage device of a plurality of storage devices are received by a storage controller. A first number of blocks of the storage device to a high resiliency portion and a second number of blocks of the storage device to a low resiliency portion of the storage device are allocated based on the one or more performance parameters.
    Type: Application
    Filed: September 1, 2023
    Publication date: December 28, 2023
    Inventors: HARI KANNAN, GORDON JAMES COLEMAN, YIJIE ZHAO, PETER E. KIRKPATRICK, ROBERT LEE, YUHONG MAO, BORIS FEIGIN
  • Patent number: 11853266
    Abstract: A system for cloud-based file services, comprising: a plurality of single-tenant file system nodes configured to provide file system access to an object store via a plurality of multitenant storage nodes; the plurality of multitenant storage nodes sharing access to the object store; and one or more management nodes configured to provision resources for the plurality of single-tenant file system nodes and the plurality of multitenant storage nodes, including modifying resources within the system.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: December 26, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Robert Lee, Igor Ostrovsky, Mark Emberson, Boris Feigin, Ronald Karr
  • Patent number: 11847324
    Abstract: A storage system establishes a staging region, for temporary writing of arriving data, and a stable region, for transfer of data from the staging region, in storage memory. The storage system establishes resiliency groups, each with a characteristic level of redundancy that is settable on an individual basis. The storage system performs data accesses of data stripes in accordance with the staging region, the stable region, a first resiliency group and a second resiliency group.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: December 19, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Robert Lee, Boris Feigin, Ying Gao, Ronald Karr
  • Publication number: 20230333781
    Abstract: A redundant array of independent drives (RAID) stripe is formed across a set of storage controllers of a plurality of storage controllers, wherein the RAID stripe comprises two or more of a plurality of modular storage devices of at least one of the set of storage controllers. The RAID stripe is written across the set of storage controllers.
    Type: Application
    Filed: June 23, 2023
    Publication date: October 19, 2023
    Inventors: HARI KANNAN, ROBERT LEE, YUHONG MAO, RONALD KARR, BORIS FEIGIN
  • Patent number: 11789626
    Abstract: One or more performance parameters associated with data stored at a storage device of a plurality of storage devices are received by a storage controller. A first number of blocks of the storage device to a high resiliency portion and a second number of blocks of the storage device to a low resiliency portion of the storage device are allocated based on the one or more performance parameters.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: October 17, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Hari Kannan, Gordon James Coleman, Yijie Zhao, Peter E. Kirkpatrick, Robert Lee, Yuhong Mao, Boris Feigin
  • Patent number: 11782625
    Abstract: A method of operating a storage system, and related storage system, are provided. The storage system establishes resiliency groups, each having a defined level of redundancy of resources of the storage system. The resiliency groups include at least one compute resources resiliency group and at least one storage resources resiliency group. The storage system supports capability of configurations that have multiples of each of the resiliency groups. Blades of the storage system perform distributed data and metadata storage across modular storage devices, in accordance with the resiliency groups.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: October 10, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Robert Lee, Boris Feigin, Ying Gao, Ronald Karr
  • Publication number: 20230281177
    Abstract: A storage system is provided. The storage system include a primary storage node that includes a primary processing device. The primary storage node is communicatively coupled to a secondary storage node. The secondary storage node includes a secondary processing device and a set of non-volatile memory modules. The primary processing device is to identify one or more storage operations to be performed on the set of non-volatile memory modules of the secondary storage node and transmit one or more instructions to the secondary storage node to perform the one or more storage operations, the one or more storage operations performed by the secondary processing device.
    Type: Application
    Filed: March 1, 2023
    Publication date: September 7, 2023
    Inventors: HARI KANNAN, YING GAO, BORIS FEIGIN, ROBERT LEE
  • Publication number: 20230251797
    Abstract: A first set of physical units of a storage device of a storage system is selected for performance of low latency access operations, wherein other access operations are performed by remaining physical units of the storage device. A determination as to whether a triggering event has occurred that causes a selection of a new set of physical units of the storage device for the performance of low latency access operations is made. A second set of physical units of the storage device is selected for the performance of low latency access operations upon determining that the triggering event has occurred.
    Type: Application
    Filed: March 27, 2023
    Publication date: August 10, 2023
    Inventors: HARI KANNAN, BORIS FEIGIN, YING GAO, JOHN COLGROVE
  • Patent number: 11714572
    Abstract: A redundant array of independent drives (RAID) stripe is formed across a set of storage controllers of a plurality of storage controllers, wherein the RAID stripe comprises two or more of a plurality of modular storage devices of at least one of the set of storage controllers. The RAID stripe is written across the set of storage controllers.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: August 1, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Hari Kannan, Robert Lee, Yuhong Mao, Ronald Karr, Boris Feigin
  • Publication number: 20230221878
    Abstract: A storage system has a first memory, and a second memory that includes storage memory. The storage system has a processing device. The processing device is to select whether to write data to the first memory and write the data from the first memory to the second memory, or to write the data to the second memory bypassing the first memory. The processing device is to write portions of data for storage according to such selection.
    Type: Application
    Filed: March 17, 2023
    Publication date: July 13, 2023
    Inventors: YING GAO, BORIS FEIGIN, HARI KANNAN, IGOR OSTROVSKY, JEFFREY TOFANO
  • Patent number: 11681448
    Abstract: Fabric modules in a storage system offer differing device IDs from a deterministic sequence to a storage device being added to the storage system. The storage device that is being added accepts a device ID that is higher in the deterministic sequence. The fabric module that offered the device ID same as was accepted by the storage device determines to proceed with initializing the storage device.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: June 20, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Ian Juch, Hao Liu, Boris Feigin, Haijie Xiao, Gordon James Coleman
  • Patent number: 11614880
    Abstract: A storage system has a first memory, and a second memory that includes storage memory. The storage system has a processing device. The processing device is to select whether to write data to the first memory and write the data from the first memory to the second memory, or to write the data to the second memory bypassing the first memory. The processing device is to write portions of data for storage according to such selection.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: March 28, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Ying Gao, Boris Feigin, Hari Kannan, Igor Ostrovsky, Jeffrey Tofano
  • Patent number: 11614893
    Abstract: A first set of physical units of a storage device of a storage system is selected for performance of low latency access operations, wherein other access operations are performed by remaining physical units of the storage device. A determination as to whether a triggering event has occurred that causes a selection of a new set of physical units of the storage device for the performance of low latency access operations is made. A second set of physical units of the storage device is selected for the performance of low latency access operations upon determining that the triggering event has occurred.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: March 28, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Hari Kannan, Boris Feigin, Ying Gao, John Colgrove
  • Publication number: 20230024480
    Abstract: One or more performance parameters associated with data stored at a storage device of a plurality of storage devices are received by a storage controller. A first number of blocks of the storage device to a high resiliency portion and a second number of blocks of the storage device to a low resiliency portion of the storage device are allocated based on the one or more performance parameters.
    Type: Application
    Filed: September 28, 2022
    Publication date: January 26, 2023
    Inventors: Hari Kannan, Gordon James Coleman, Yijie Zhao, Peter E. Kirkpatrick, Robert Lee, Yuhong Mao, Boris Feigin
  • Publication number: 20220358097
    Abstract: A system for cloud-based file services, comprising: a plurality of single-tenant file system nodes configured to provide file system access to an object store via a plurality of multitenant storage nodes; the plurality of multitenant storage nodes sharing access to the object store; and one or more management nodes configured to provision resources for the plurality of single-tenant file system nodes and the plurality of multitenant storage nodes, including modifying resources within the system.
    Type: Application
    Filed: July 18, 2022
    Publication date: November 10, 2022
    Inventors: ROBERT LEE, IGOR OSTROVSKY, MARK EMBERSON, BORIS FEIGIN, RONALD KARR
  • Patent number: 11487455
    Abstract: One or more performance parameters associated with data stored at a storage device of a plurality of storage devices are received by a storage controller. A first number of blocks of the storage device to a high resiliency portion and a second number of blocks of the storage device to a low resiliency portion of the storage device are allocated based on the one or more performance parameters.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: November 1, 2022
    Assignee: Pure Storage, Inc.
    Inventors: Hari Kannan, Gordon James Coleman, Yijie Zhao, Peter E. Kirkpatrick, Robert Lee, Yuhong Mao, Boris Feigin
  • Publication number: 20220300193
    Abstract: A storage system has NVRAM (nonvolatile random-access memory), storage memory that includes SLC (single level cell) flash memory and QLC (quad level cell) flash memory, and a processor. The processor performs a method that includes selecting one of a plurality of write paths for incoming data, and writing the incoming data via the selected write path. A first write path includes writing to NVRAM, writing from NVRAM to SLC flash memory and writing from SLC flash memory to QLC flash memory. A second write path includes writing to NVRAM and writing from NVRAM to QLC flash memory, bypassing SLC flash memory. A third write path includes writing to SLC flash memory, bypassing NVRAM, and writing from SLC flash memory to QLC flash memory.
    Type: Application
    Filed: June 2, 2022
    Publication date: September 22, 2022
    Inventors: Ying Gao, Boris Feigin, Hari Kannan
  • Publication number: 20220300198
    Abstract: A storage system has NVRAM (nonvolatile random-access memory), storage memory that includes SLC (single level cell) flash memory and QLC (quad level cell) flash memory, and a processor. The processor performs a method that includes determining that a size of a buffer of a storage system should be adjusted. The storage system comprises a non-volatile random-access memory (NVRAM), single level cell (SLC) flash memory, and quad level cell (QLC) flash memory. The buffer of the storage system comprises one or more of the NVRAM and a portion of the SLC flash memory. The method also includes adjusting the size of the buffer of the storage system to a first size.
    Type: Application
    Filed: June 3, 2022
    Publication date: September 22, 2022
    Inventors: Ying Gao, Boris Feigin, Hari Kannan