Patents by Inventor Boris Gedzberg

Boris Gedzberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low cost metallization during fabrication of an integrated circuit (IC)
    Patent number: 11081442
    Abstract: A method for metallization during fabrication of an Integrated Circuit (IC). The IC includes a semiconductor wafer having a back surface and a front surface. The method includes etching a via hole through the semiconductor wafer. After this, a seed metal layer is deposited on the back surface of the semiconductor wafer. Thereafter, a photoresist layer is deposited on the back surface of the semiconductor wafer such that the via hole remains uncovered. After depositing the photoresist layer, a metal layer is formed along the walls of the via hole to electrically connect the back surface and the front surface of the semiconductor wafer. Finally, the photoresist layer is removed subsequent to forming the metal layer.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: August 3, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventors: Mohsen Shokrani, Boris Gedzberg, Ronald L. Michels
  • LOW COST METALLIZATION DURING FABRICATION OF AN INTEGRATED CIRCUIT (IC)
    Publication number: 20200126902
    Abstract: A method for metallization during fabrication of an Integrated Circuit (IC). The IC includes a semiconductor wafer having a back surface and a front surface. The method includes etching a via hole through the semiconductor wafer. After this, a seed metal layer is deposited on the back surface of the semiconductor wafer. Thereafter, a photoresist layer is deposited on the back surface of the semiconductor wafer such that the via hole remains uncovered. After depositing the photoresist layer, a metal layer is formed along the walls of the via hole to electrically connect the back surface and the front surface of the semiconductor wafer. Finally, the photoresist layer is removed subsequent to forming the metal layer.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 23, 2020
    Inventors: Mohsen Shokrani, Boris Gedzberg, Ronald L. Michels
  • Low cost metallization during fabrication of an integrated circuit (IC)
    Patent number: 10461025
    Abstract: A method for metallization during fabrication of an Integrated Circuit (IC). The IC includes a semiconductor wafer having a back surface and a front surface. The method includes etching a via hole through the semiconductor wafer. After this, a seed metal layer is deposited on the back surface of the semiconductor wafer. Thereafter, a photoresist layer is deposited on the back surface of the semiconductor wafer such that the via hole remains uncovered. After depositing the photoresist layer, a metal layer is formed along the walls of the via hole to electrically connect the back surface and the front surface of the semiconductor wafer. Finally, the photoresist layer is removed subsequent to forming the metal layer.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: October 29, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Mohsen Shokrani, Boris Gedzberg, Ronald Michels
  • LOW COST METALLIZATION DURING FABRICATION OF AN INTEGRATED CIRCUIT (IC)
    Publication number: 20190244890
    Abstract: A method for metallization during fabrication of an Integrated Circuit (IC). The IC includes a semiconductor wafer having a back surface and a front surface. The method includes etching a via hole through the semiconductor wafer. After this, a seed metal layer is deposited on the back surface of the semiconductor wafer. Thereafter, a photoresist layer is deposited on the back surface of the semiconductor wafer such that the via hole remains uncovered. After depositing the photoresist layer, a metal layer is formed along the walls of the via hole to electrically connect the back surface and the front surface of the semiconductor wafer. Finally, the photoresist layer is removed subsequent to forming the metal layer.
    Type: Application
    Filed: January 2, 2019
    Publication date: August 8, 2019
    Inventors: Mohsen Shokrani, Boris Gedzberg, Ron Michels
  • Low cost metallization during fabrication of an integrated circuit (IC)
    Patent number: 10199324
    Abstract: A method for metallization during fabrication of an Integrated Circuit (IC). The IC includes a semiconductor wafer having a back surface and a front surface. The method includes etching a via hole through the semiconductor wafer. After this, a seed metal layer is deposited on the back surface of the semiconductor wafer. Thereafter, a photoresist layer is deposited on the back surface of the semiconductor wafer such that the via hole remains uncovered. After depositing the photoresist layer, a metal layer is formed along the walls of the via hole to electrically connect the back surface and the front surface of the semiconductor wafer. Finally, the photoresist layer is removed subsequent to forming the metal layer.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: February 5, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Mohsen Shokrani, Boris Gedzberg, Ron Michels
  • Structures and methods for fabricating vertically integrated HBT-FET device
    Patent number: 7718486
    Abstract: Methods and systems for fabricating integrated pairs of HBT/FET's are disclosed. One preferred embodiment comprises a method of fabricating an integrated pair of GaAs-based HBT and FET. The method comprises the steps of: growing a first set of epitaxial layers for fabricating the FET on a semi-insulating GaAs substrate; fabricating a highly doped thick GaAs layer serving as the cap layer for the FET and the subcollector layer for the HBT; and producing a second set of epitaxial layers for fabricating the HBT.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: May 18, 2010
    Assignee: Anadigics, Inc.
    Inventors: Oleh Krutko, Kezhou Xie, Mohsen Shokrani, Aditya Gupta, Boris Gedzberg
  • Structures and methods for fabricating vertically integrated HBT-FET device
    Publication number: 20060113566
    Abstract: Methods and systems for fabricating integrated pairs of HBT/FET's are disclosed. One preferred embodiment comprises a method of fabricating an integrated pair of GaAs-based HBT and FET. The method comprises the steps of: growing a first set of epitaxial layers for fabricating the FET on a semi-insulating GaAs substrate; fabricating a highly doped thick GaAs layer serving as the cap layer for the FET and the subcollector layer for the HBT; and producing a second set of epitaxial layers for fabricating the HBT.
    Type: Application
    Filed: January 13, 2006
    Publication date: June 1, 2006
    Inventors: Oleh Krutko, Kezhou Xie, Mohsen Shokrani, Aditya Gupta, Boris Gedzberg
  • Structures and methods for fabricating vertically integrated HBT/FET device
    Patent number: 7015519
    Abstract: Methods and systems for fabricating integrated pairs of HBT/FET's are disclosed. One preferred embodiment comprises a method of fabricating an integrated pair of GaAs-based HBT and FET. The method comprises the steps of: growing a first set of epitaxial layers for fabricating the FET on a semi-insulating GaAs substrate; fabricating a highly doped thick GaAs layer serving as the cap layer for the FET and the subcollector layer for the HBT; and producing a second set of epitaxial layers for fabricating the HBT.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: March 21, 2006
    Assignee: Anadigics, Inc.
    Inventors: Oleh Krutko, Kezhou Xie, Mohsen Shokrani, Aditya Gupta, Boris Gedzberg
  • Structures and methods for fabricating integrated HBT/FET's at competitive cost
    Publication number: 20050184310
    Abstract: Methods and systems for fabricating integrated pairs of HBT/FET's are disclosed. One preferred embodiment comprises a method of fabricating an integrated pair of GaAs-based HBT and FET. The method comprises the steps of: growing a first set of epitaxial layers for fabricating the FET on a semi-insulating GaAs substrate; fabricating a highly doped thick GaAs layer serving as the cap layer for the FET and the subcollector layer for the HBT; and producing a second set of epitaxial layers for fabricating the HBT.
    Type: Application
    Filed: February 20, 2004
    Publication date: August 25, 2005
    Inventors: Oleh Krutko, Kezhou Xie, Mohsen Shokrani, Aditya Gupta, Boris Gedzberg