Abstract: In one embodiment, the present invention includes a device that has a device processor and a device memory. The device can couple to a host with a host processor and host memory. Both of the memories can have page tables to map virtual addresses to physical addresses of the corresponding memory, and the two memories may appear to a user-level application as a single virtual memory space. Other embodiments are described and claimed.

Abstract: Embodiments of the present invention provide a method for selectively modulating a data frame of a signal using either a frequency-multiplexing modulation method or a spatial-multiplexing modulation method based on a predetermined criterion.

Abstract: In one embodiment, the present invention includes a device that has a device processor and a device memory. The device can couple to a host with a host processor and host memory. Both of the memories can have page tables to map virtual addresses to physical addresses of the corresponding memory, and the two memories may appear to a user-level application as a single virtual memory space. Other embodiments are described and claimed.

Abstract: A processor may support a two-dimensional (2-D) gather instruction and a 2-D cache. The processor may perform the 2-D gather instruction to access one or more sub-blocks of data from a two-dimensional (2-D) image stored in a memory coupled to the processor. The two-dimensional (2-D) cache may store the sub-blocks of data in a multiple cache lines. Further, the 2-D cache may support access of more than one cache lines while preserving a two-dimensional structure of the 2-D image.

Abstract: A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a graphics processing unit to secure a mutex for a shared memory.

Abstract: A computer system may support one or more techniques to allow dynamic pinning of the memory pages accessed by a non-CPU device (e.g., a graphics processing unit, GPU). The non-CPU may support virtual to physical address mapping and may thus be aware of the memory pages, which may not be pinned but may be accessed by the non-CPU. The non-CPU may notify or send such information to a run-time component such as a device driver associated with the CPU. In one embodiment, the device driver may, dynamically, perform pinning of such memory pages, which may be accessed by the non-CPU. The device driver may even unpin the memory pages, which may be no longer accessed by the non-CPU. Such an approach may allow the memory pages, which may be no longer accessed by the non-CPU to be available for allocation to the other CPUs and/or non-CPUs.

Abstract: A method for detection of underground anomalies including in a system of distributed antennas (10), which are leaky transmission lines, disposed in 16 boreholes (12) formed in a ground, a transmitter (14) being connected to one of the antennas (10), and a receiver (16) being connected to another of the antennas (10), injecting an electromagnetic pulse into one of the antennas (10), wherein the pulse gradually leaks out, and wherein if a speed of propagation in the line in which the pulse is injected is faster than a speed of propagation in the ground, a shock wave is transmitted through the ground, called a transmitted signal, and received as a received signal at another of the antennas (10), and wherein an underground anomaly diffracts the shock wave, resulting in a detectable disturbance in the received signal, and locating the anomaly as a function of a time delay of the disturbance relative to the transmitted signal.

Abstract: Solvent and acid stable ultrafiltration and nanofiltration membranes including a non-cross-linked base polymer having reactive pendant moieties, the base polymer being modified by forming a cross-linked skin onto a surface thereof, the skin being formed by a cross-linking reaction of reactive pendant moieties on the surface with an oligomer or another polymer as well as methods of manufacture and use thereof, including, inter alia separating metal ions from liquid process streams.

Abstract: Page faults arising in a graphics processing unit may be handled by an operating system running on the central processing unit. In some embodiments, this means that unpinned memory can be used for the graphics processing unit. Using unpinned memory in the graphics processing unit may expand the capabilities of the graphics processing unit in some cases.

Abstract: Page faults arising in a graphics processing unit may be handled by an operating system running on the central processing unit. In some embodiments, this means that unpinned memory can be used for the graphics processing unit. Using unpinned memory in the graphics processing unit may expand the capabilities of the graphics processing unit in some cases.

Abstract: A method, algorithm, software, architecture and/or system for routing signal paths or connections between circuit blocks in a circuit design is disclosed. In one embodiment, a method of routing can include: (i) determining a signal path between at least three circuit blocks; (ii) placing a routing guide; and (iii) routing the signal path through the routing guide such that a timing of a signal along the signal path at two or more the circuit blocks is substantially matched. The circuit blocks can include standard cells configured to implement a logic or timing function, other components, and/or integrated circuits, for example. The routing guide can include a splitter configured to branch the signal path into at least two associated segments. Embodiments of the present invention can advantageously improve signal timing for high fanout signal paths between circuit blocks in an automated place-and-route flow.

Abstract: An embodiment of the present invention provides an apparatus, comprising a network adapter configured for wireless communication using more than one technology, and wherein the network adapter is configured to share a plurality of shared hardware components by limiting access to the air to one comm only at given time by designating one comm that owns the shared hardware components as a primary comm and all other comms are secondary comms, wherein the primary comm allows the secondary comms to use the shared hardware components when it is in an idle-state but when the primary comm returns from the idle state, it claims ownership of the shared resources and the secondary comms release the shared resources.

Abstract: Embodiments of the present invention provide a method and apparatus for a multiple-entity wireless communication adapter, including at least a first connection module to communicate first signal traffic corresponding to a basic service set station entity, a second connection module to communicate second signal traffic corresponding to an entity that is not a basic service set station, and a shared physical layer able to process both the first and the second signal traffic. Additional features are described and claimed.

Abstract: An embodiment of the present invention provides an apparatus, comprising a network adapter configured for wireless communication using more than one technology, and wherein the network adapter is configured to share a plurality of shared hardware components by limiting access to the air to one comm only at given time by designating one comm that owns the shared hardware components as a primary comm and all other comms are secondary comms, wherein the primary comm allows the secondary comms to use the shared hardware components when it is in an idle-state but when the primary comm returns from the idle state, it claims ownership of the shared resources and the secondary comms release the shared resources.

Abstract: A method, algorithm, software, architecture and/or system for routing signal paths or connections between circuit blocks in a circuit design is disclosed. In one embodiment, a method of routing can include: (i) determining a signal path between at least three circuit blocks; (ii) placing a routing guide; and (iii) routing the signal path through the routing guide such that a timing of a signal along the signal path at two or more the circuit blocks is substantially matched. The circuit blocks can include standard cells configured to implement a logic or timing function, other components, and/or integrated circuits, for example. The routing guide can include a splitter configured to branch the signal path into at least two associated segments. Embodiments of the present invention can advantageously improve signal timing for high fanout signal paths between circuit blocks in an automated place-and-route flow.

Abstract: A method, algorithm, software, architecture and/or system for routing signal paths or connections between circuit blocks in a circuit design is disclosed. In one embodiment, a method of routing can include: (i) determining a signal path between at least three circuit blocks; (ii) placing a routing guide; and (iii) routing the signal path through the routing guide such that a timing of a signal along the signal path at two or more the circuit blocks is substantially matched. The circuit blocks can include standard cells configured to implement a logic or timing function, other components, and/or integrated circuits, for example. The routing guide can include a splitter configured to branch the signal path into at least two associated segments. Embodiments of the present invention can advantageously improve signal timing for high fanout signal paths between circuit blocks in an automated place-and-route flow.

Abstract: A method, algorithm, software, architecture and/or system for placing circuit blocks and routing signal paths or connections between the circuit blocks in a circuit design is disclosed. In one embodiment, a method of placing and routing can include: (i) routing signal paths in one or more upper metal layers for connecting circuit blocks; (ii) adjusting the circuit blocks based on electrical characteristics of the signal paths; and (iii) routing in one or more lower metal layers connections between the circuit blocks and the upper layers. The circuit blocks can include standard cells, blocks, or gates configured to implement a logic or timing function, other components, and/or integrated circuits, for example. Embodiments of the present invention can advantageously reduce power consumption and improve timing closure in an automated place-and-route flow.

Abstract: An apparatus and method are described for multiplying and adding matrices. For example, one embodiment of a method comprises decoding by a decoder in a processor device, a single instruction specifying an m-by-m matrix operation for a set of vectors, wherein each vector represents an m-by-m matrix of data elements and m is greater than one; issuing the single instruction for execution by an execution unit in the processor device; and responsive to the execution of the single instruction, generating a resultant vector, wherein the resultant vector represents an m-by-m matrix of data elements.

Abstract: A method and apparatus for adaptive network allocation are described herein. In some embodiments, a node may receive a request-to-send (RTS) packet that includes duration information and a basic service set identifier (BSSID). The network node may update a network allocation vector based at least in part on a received signal strength of the RTS packet and the BSSID. Other embodiments may be described and claimed.

Abstract: In one embodiment, the present invention includes a device that has a device processor and a device memory. The device can couple to a host with a host processor and host memory. Both of the memories can have page tables to map virtual addresses to physical addresses of the corresponding memory, and the two memories may appear to a user-level application as a single virtual memory space. Other embodiments are described and claimed.