Patents by Inventor Boris Zapesochini

Boris Zapesochini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Connection quality verification for integrated circuit test
    Patent number: 9097758
    Abstract: An integrated circuit device comprising a semiconductor die contained in a package. The integrated circuit device includes one or more internal connection verification modules for asserting a poor connection signal for the test apparatus in response to a voltage difference between a voltage at a corresponding internal power supply node and a reference voltage, the voltage difference being indicative of a poor connection of power supply to one of power supply terminals on the package. The test apparatus can include an indicator or a sorting element for rejecting or accepting the integrated circuit device in response to logic signals indicative of the presence or absence of a defect accompanied by non-assertion of the poor connection signal, and for processing the integrated circuit device distinctively in response to assertion of the poor connection signal.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: August 4, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yefim-Haim Fefer, Sergey Sofer, Boris Zapesochini
  • CONNECTION QUALITY VERIFICATION FOR INTEGRATED CIRCUIT TEST
    Publication number: 20120038367
    Abstract: An integrated circuit device comprising a semiconductor die contained in a package. The integrated circuit device includes one or more internal connection verification modules for asserting a poor connection signal for the test apparatus in response to a voltage difference between a voltage at a corresponding internal power supply node and a reference voltage, the voltage difference being indicative of a poor connection of power supply to one of power supply terminals on the package. The test apparatus can include an indicator or a sorting element for rejecting or accepting the integrated circuit device in response to logic signals indicative of the presence or absence of a defect accompanied by non-assertion of the poor connection signal, and for processing the integrated circuit device distinctively in response to assertion of the poor connection signal.
    Type: Application
    Filed: March 31, 2009
    Publication date: February 16, 2012
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Yefim-Haim Fefer, Sergey Sofer, Boris Zapesochini