Abstract: A method of initializing a Fiber Channel over Ethernet (FCoE) link between a Fiber Channel over Ethernet node (ENode) and Fiber Channel Forwarders (FCFs) in a network by discovering the presence of FCFs available to the ENode and other FCFs, assigning second MAC addresses to the ENode corresponding to each available FCF, and converting from a management and initialization process using the first MAC address to normal Fiber Channel operation using the second MAC addresses. The implementations described herein may additionally distinguish management and initialization processes from normal Fiber Channel operation using separate Ethertypes.

Abstract: An apparatus comprising a circuit configured to translate instruction codes of a first instruction set into sequences of instruction codes of a second instruction set that emulate a functionality of the instruction codes of the first instruction set.

Abstract: A method of initializing a Fibre Channel over Ethernet (FCoE) link between a Fibre Channel over Ethernet node (ENode) and Fibre Channel Forwarders (FCFs) in a network by discovering the presence of FCFs available to the ENode and other FCFs, assigning second MAC addresses to the ENode corresponding to each available FCF, and converting from a management and initialization process using the first MAC address to normal Fibre Channel operation using the second MAC addresses. The implementations described herein may additionally distinguish management and initialization processes from normal Fibre Channel operation using separate Ethertypes.

Abstract: A network interface card comprising an upper layer protocol (ULP) handler, a TCP handler capable of interfacing with said ULP handler and, a link handler. The network interface card is adapted to take over and perform at least one session layer function of a host computer connected to a network.

Abstract: An apparatus comprising a processor and a translator circuit. The processor may (i) comprise a number of internal registers and (ii) be configured to manipulate contents of the internal registers in response to instruction codes of a first instruction set. The translator circuit may be configured to implement a stack using one or more of the internal registers of the processor.

Abstract: A network interface card comprising an upper layer protocol (ULP) handler, a TCP handler capable of interfacing with said ULP handler and, a link handler. The network interface card is adapted to take over and perform at least one session layer function of a host computer connected to a network.

Abstract: An apparatus comprising a translator circuit and a cache. The translator circuit may be configured to (i) translate one or more first instruction codes of a first instruction set into second instruction codes of a second instruction set, (ii) present the second instruction codes to a processor, and (iii) allow interrupts to the processor to be handled seamlessly.

Abstract: An apparatus comprising a circuit configured to (i) translate one or more instruction codes of a first instruction set into a sequence of instruction codes of a second instruction set and (ii) present the sequence of instruction codes of the second instruction set in response to a predetermined number of addresses.

Abstract: Clock cycle simulation involves modeling of clock cycles in a hardware module with a software model. Each simulated clock cycle involves several individual stages: Start, Execute, and End. During the start stage, output pin values for the model are calculated from an initial state of the module being simulated. Between the start stage and the execution stage, a combinatorial function of the modules outputs can be calculated. These calculated functions may be used as inputs to the modules in the execution stage. Afterwards, during the execute stage, input pin values are received by the model and the next state of the module is calculated based upon the current module state and the input pin values. Finally, during the last stage, i.e., the end stage, the internal state is updated; the internal state is defined as a set of the module's internal register and memory values.

Abstract: An apparatus comprising one or more first processors and one or more second processors. The one or more first processors may each comprise a first random access memory (RAM) sections. The one or more second processors may each comprise a read only memory (ROM) section and a second RAM section. The one or more first processors may be configured to operate in either (i) a first mode that executes code stored in the one or more ROM sections or (ii) a second mode that processes code stored in the one or more first RAM sections. The one or more second processors may be configured to execute code from either (i) the one or more ROM sections or (ii) the one or more second RAM sections. The apparatus may provide interoperability that may increase system observability and decrease system debugging complexity.