Abstract: Circuits embodying the invention include apparatus for sensing the amplitude and the frequency of the signals received from one section of a telephone cable and for propagating onto the succeeding section of telephone cable only those received signals having an amplitude greater than a predetermined level and whose frequency is within the predetermined range.

Abstract: A timing circuit is described which includes a storage capacitor, a switch, and a load to be energized in a closed loop. A programmable timer, energized by the storage capacitor controls the switch. An external potential is applied to charge the capacitor and hold the timer in a reset mode. Upon removal of the external potential the timer is enabled and closes the switch a predetermined time thereafter.

Abstract: First, second and third set-reset flip-flops (FFs), reset to an initial stable state, are interconnected such that the second FF can change state only after the first FF has changed state and the third FF can change state only after the second FF has changed state. Outputs of the first and second FFs are combined to enable the production of a first output pulse and outputs of the second and third FFs are combined to enable the production of a second output pulse consecutive to, and non-overlapping with, the first output pulse.

Abstract: A circuit for preventing the simultaneous application of contradictory input commands to a system and for filtering-out signals of shorter duration than a given period. The circuit includes an EXCLUSIVE-OR type gate adapted to receive input commands, whose output is "True" only when one of the input commands is present and no contradictory condition exists. The output of the gate is coupled to the input of a first flip flop which is set to a state indicative of the presence of the "True" signal at its input, when clocked at some time t.sub.1. The output of the first flip flop is logically combined with the one input command that is present to produce a signal which is applied to the input of a second flip flop. The second flip flop is placed in a state indicative of the value of its input, when clocked at some time t.sub.2, subsequent to t.sub.1. The one input command must be present for the duration t.sub.1 -t.sub.2 to place the second flip flop in its set state.

Abstract: A flip-flop comprising two, cross-coupled, transistors each having one end of its main conduction path connected to a common current source, and in which switching between states is accomplished by the application of voltages coupled through voltage dropping resistors connected to the other ends of the main conduction paths of the two transistors. The circuitry for applying the switching voltages includes an emitter-coupled logic (ECL) gate comprising a differential amplifier stage containing a pulse forming network for producing a sampling pulse at one output and a clocking signal at another output. The sampling pulse is "AND'ed" with input data signals to set the flip-flop to one binary condition and the clocking signal is used to reset the flip-flop to the other binary condition. Circuitry for sensing the state of the flip-flop includes a differential stage whose inputs are coupled to the control electrodes of the transistors of the flip-flop.

Abstract: An emitter coupled logic (ECL) circuit for producing noncomplementary, time coincident signals. The circuit includes a differential amplifier stage having first and second inputs and first and second outputs with a pulse forming network coupled between the two outputs. In response to an input signal applied between the inputs, the voltage at the first output makes a transition from a first level to a second level and the voltage at the second output makes a transition from the second level to the first level. The network, in response to the changes in the voltage levels at the outputs, causes the restoration of the first level at the first output a given time delay after its transition to the second level, notwithstanding the presence of the input signal.

Abstract: Successively larger fractions of a first composite signal are compared with an entire second composite signal to obtain control signals. The composite signals comprise similar direct components with push-pull a-c signals superimposed thereon. One of these control signals may be used to standardize the average amplitude of the push-pull signals by causing them to be attenuated when they exceed a given amplitude, and at least one other, for controlling the synchronous regeneration of the a-c signals. The invention is useful for PCM repeaters in telephone cables.