Patents by Inventor Bo-Wei Hsieh
Bo-Wei Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11989005Abstract: A system performs adaptive thermal ceiling control at runtime. The system includes computing circuits and a thermal management module. When detecting a runtime condition change that affects power consumption in the system, the thermal management module determines an adjustment to the thermal ceiling of a computing circuit, and increases the thermal ceiling of the computing circuit according to the adjustment.Type: GrantFiled: September 30, 2021Date of Patent: May 21, 2024Assignee: MediaTek Inc.Inventors: Bo-Jr Huang, Jia-Wei Fang, Jia-Ming Chen, Ya-Ting Chang, Chien-Yuan Lai, Cheng-Yuh Wu, Yi-Pin Lin, Wen-Wen Hsieh, Min-Shu Wang
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Patent number: 11776613Abstract: A training method for a memory system is provided. The memory system includes a memory controller and a memory. The memory controller is connected with the memory. The training method includes the following steps. Firstly, the memory samples n command/address signals according to a first signal edge and a second signal edge of a clock signal to acquire a first sampled content and a second sampled content. The memory selectively outputting one of the first sampled content and the second sampled content through m data signals to the memory controller in response to a control signal. Moreover, m is larger than n and smaller than 2n.Type: GrantFiled: April 22, 2021Date of Patent: October 3, 2023Assignee: MediaTek Inc.Inventors: Bo-Wei Hsieh, Ching-Yeh Hsuan, Shang-Pin Chen
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Publication number: 20230289063Abstract: An electronic system is provided. A memory device includes a plurality of bank groups. A controller is coupled to the memory device and includes a request queue. The request queue is configured to store a plurality of requests. When the requests correspond to the different bank groups, the controller is configured to access data of the memory device according to a plurality of long burst commands corresponding to the requests. When the requests correspond to the same bank group, the controller is configured to access the data of the memory device according to a plurality of short burst commands corresponding to the requests. The short burst commands correspond to a short burst length, and the long burst commands correspond to a long burst length. The long burst length is twice the short burst length. The memory device is a low-power double data rate synchronous dynamic random access memory.Type: ApplicationFiled: February 16, 2023Publication date: September 14, 2023Inventors: Bo-Wei HSIEH, Chen-Chieh WANG, Szu-Ying CHENG, Jou-Ling CHEN
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Patent number: 11373692Abstract: A delay tracking method and a memory system are provided. The delay tracking method is applied to a memory system supporting a low-frequency-mode (LFM) and a high-frequency-mode (HFM) of an operating clock. The delay tracking method includes the steps of selecting a LFM oscillator for obtaining a LFM delay value when the operating clock is in the HFM; and selecting a HFM oscillator for obtaining a HFM delay value when the operating clock is in the LFM.Type: GrantFiled: February 19, 2021Date of Patent: June 28, 2022Assignee: MediaTek Inc.Inventors: Bo-Wei Hsieh, Chia-Yu Chan, Jou-Ling Chen
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Publication number: 20210295894Abstract: A training method for a memory system is provided. The memory system includes a memory controller and a memory. The memory controller is connected with the memory. The training method includes the following steps. Firstly, the memory samples n command/address signals according to a first signal edge and a second signal edge of a clock signal to acquire a first sampled content and a second sampled content. The memory selectively outputting one of the first sampled content and the second sampled content through m data signals to the memory controller in response to a control signal. Moreover, m is larger than n and smaller than 2n.Type: ApplicationFiled: April 22, 2021Publication date: September 23, 2021Applicant: MediaTek Inc.Inventors: Bo-Wei Hsieh, Ching-Yeh Hsuan, Shang-Pin Chen
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Publication number: 20210174851Abstract: A delay tracking method and a memory system are provided. The delay tracking method is applied to a memory system supporting a low-frequency-mode (LFM) and a high-frequency-mode (HFM) of an operating clock. The delay tracking method includes the steps of selecting a LFM oscillator for obtaining a LFM delay value when the operating clock is in the HFM; and selecting a HFM oscillator for obtaining a HFM delay value when the operating clock is in the LFM.Type: ApplicationFiled: February 19, 2021Publication date: June 10, 2021Applicant: Media Tek Inc.Inventors: Bo-Wei Hsieh, Chia-Yu Chan, Jou-Ling Chen
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Patent number: 11017839Abstract: A training method for a memory system is provided. The memory system includes a memory controller and a memory. The memory controller is connected with the memory. The training method includes the following steps. Firstly, the memory samples n command/address signals according to a first signal edge and a second signal edge of a clock signal to acquire a first sampled content and a second sampled content. The memory selectively outputting one of the first sampled content and the second sampled content through m data signals to the memory controller in response to a control signal. Moreover, m is larger than n and smaller than 2n.Type: GrantFiled: January 5, 2018Date of Patent: May 25, 2021Assignee: MediaTek Inc.Inventors: Bo-Wei Hsieh, Ching-Yeh Hsuan, Shang-Pin Chen
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Patent number: 10964363Abstract: A delay tracking method and a memory system are provided. The delay tracking method is applied to a memory system supporting a low-frequency-mode (LFM) and a high-frequency-mode (HFM) of an operating clock. The delay tracking method includes the steps of selecting a LFM oscillator for obtaining a LFM delay value when the operating clock is in the HFM; and selecting a HFM oscillator for obtaining a HFM delay value when the operating clock is in the LFM.Type: GrantFiled: August 14, 2019Date of Patent: March 30, 2021Assignee: MediaTek Inc.Inventors: Bo-Wei Hsieh, Chia-Yu Chan, Jou-Ling Chen
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Patent number: 10878879Abstract: A refresh control method for a memory controller of a memory system is provided. The memory controller is connected with a memory. The memory includes plural memory banks. The refresh control method includes the following steps. Firstly, a refresh state of the memory device is read, and thus a refresh window is realized. Then, a refresh command is issued to the memory device according to the refresh state. The refresh command contains a memory bank number field and a memory bank count field. The memory bank count field indicates a first count. The first count of memory banks are selected from the plural memory banks of the memory device according to the memory bank number field and the first count. Moreover, a refresh operation is performed on the first count of memory banks.Type: GrantFiled: June 19, 2018Date of Patent: December 29, 2020Assignee: MediaTek Inc.Inventors: Der-Ping Liu, Bo-Wei Hsieh
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Patent number: 10846018Abstract: A memory system includes a memory controller, a first memory device and a second memory device. The memory controller issues a first clock signal and a second clock signal. The memory controller transmits or receives a data signal. The first memory device receives the first clock signal and the second clock signal. The second memory device receives the first dock signal and the second clock signal. If a first mode register of the first memory device is in a first single-ended mode and a second mode register of the second memory device is in a second single-ended mode, the first memory device transmits or receives the data signal according to the first dock signal, and the second memory device transmits or receives the data signal according to the second clock signal.Type: GrantFiled: March 26, 2018Date of Patent: November 24, 2020Assignee: MEDIATEK INC.Inventors: Bo-Wei Hsieh, Chia-Yu Chan, Shang-Pin Chen
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Patent number: 10810078Abstract: A method of parity training for a dynamic random access memory, DRAM, is disclosed. The method comprises enabling a link error checking and correcting, ECC, functionality in a write operation of the DRAM, and remapping a parity function of a write parity pin to an data inversion function, a data replacing function, or a logical function, whereby data transferred to the DRAM through the write parity pin is used for indicating an inversion operation, a logical operation, or a substitution operation for data of a data pin.Type: GrantFiled: July 2, 2019Date of Patent: October 20, 2020Assignee: MEDIATEK INC.Inventors: Bo-Wei Hsieh, Chia-Yu Chan, Ching-Yeh Hsuan, Jou-Ling Chen
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Publication number: 20200058335Abstract: A delay tracking method and a memory system are provided. The delay tracking method is applied to a memory system supporting a low-frequency-mode (LFM) and a high-frequency-mode (HFM) of an operating clock. The delay tracking method includes the steps of selecting a LFM oscillator for obtaining a LFM delay value when the operating clock is in the HFM; and selecting a HFM oscillator for obtaining a HFM delay value when the operating clock is in the LFM.Type: ApplicationFiled: August 14, 2019Publication date: February 20, 2020Inventors: Bo-Wei HSIEH, Chia-Yu CHAN, Jou-Ling CHEN
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Publication number: 20200012558Abstract: A method of parity training for a dynamic random access memory, DRAM, is disclosed. The method comprises enabling a link error checking and correcting, ECC, functionality in a write operation of the DRAM, and remapping a parity function of a write parity pin to an data inversion function, a data replacing function, or a logical function, whereby data transferred to the DRAM through the write parity pin is used for indicating an inversion operation, a logical operation, or a substitution operation for data of a data pin.Type: ApplicationFiled: July 2, 2019Publication date: January 9, 2020Inventors: Bo-Wei Hsieh, Chia-Yu Chan, Ching-Yeh Hsuan, Jou-Ling Chen
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Publication number: 20190074051Abstract: A refresh control method for a memory system is provided. The memory system includes a dynamic random access memory with a register set and a memory cell array. The refresh control method includes the following steps. Firstly, a masking command or an unmasking command is issued, and thus the register set is updated. A first region of the memory cell array is set as a masked region according to the masking command. A second region of the memory cell array is set as an unmasked region according to the unmasking command. Then, a refresh command is issued to the dynamic random access memory. According to the refresh command, a refresh action is performed on the second region of the memory cell array.Type: ApplicationFiled: June 1, 2018Publication date: March 7, 2019Inventors: Chia-Fu CHANG, Hsiang-I HUANG, Bo-Wei HSIEH, Szu-Ying CHENG, Yu-Hsien TSAI
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Publication number: 20180374533Abstract: A refresh control method for a memory controller of a memory system is provided. The memory controller is connected with a memory. The memory includes plural memory banks. The refresh control method includes the following steps. Firstly, a refresh state of the memory device is read, and thus a refresh window is realized. Then, a refresh command is issued to the memory device according to the refresh state. The refresh command contains a memory bank number field and a memory bank count field. The memory bank count field indicates a first count. The first count of memory banks are selected from the plural memory banks of the memory device according to the memory bank number field and the first count. Moreover, a refresh operation is performed on the first count of memory banks.Type: ApplicationFiled: June 19, 2018Publication date: December 27, 2018Inventors: Der-Ping Liu, Bo-Wei Hsieh
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Patent number: 10163485Abstract: A memory module includes a memory interface circuit and a training signal generator. The memory interface circuit includes a plurality of terminals for communicating with a memory controller, and the terminals comprise at least a plurality of data terminals. The training signal generator is coupled to the memory interface circuit, and is arranged for generating a training signal to the memory controller through only a portion of the data terminals or a specific terminal instead of the data terminals when the memory module receives a training request from the memory controller.Type: GrantFiled: April 6, 2017Date of Patent: December 25, 2018Assignee: MEDIATEK INC.Inventors: Shang-Pin Chen, Bo-Wei Hsieh
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Patent number: 10141044Abstract: A memory interface circuit includes a plurality of receivers and a signal detector. The plurality of receivers are arranged for receiving at least a clock signal and a plurality of command signals from a memory controller, respectively. The signal detector is arranged for detecting whether the memory interface circuit receives the clock signal or not to generate a detection result to enable or disable the plurality of receivers.Type: GrantFiled: August 25, 2016Date of Patent: November 27, 2018Assignee: MEDIATEK INC.Inventors: Shang-Pin Chen, Chia-Yu Chan, Bo-Wei Hsieh
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Patent number: 10109341Abstract: A memory controller is connected with a memory. The memory controller includes a clock signal pin and plural command pins. The clock signal pin is connected with the memory for transmitting a clock signal to the memory. The plural command pins are connected with the memory for transmitting a command signal to the memory. The command signal contains an entering self-refresh command and an entering power down command. The memory enters a self-refresh state when the entering self-refresh command is executed. The memory enters a power down state when the entering power down command is executed.Type: GrantFiled: October 20, 2016Date of Patent: October 23, 2018Assignee: MEDIATEK INC.Inventors: Bo-Wei Hsieh, Shang-Pin Chen
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Publication number: 20180293026Abstract: A memory system includes a memory controller, a first memory device and a second memory device. The memory controller issues a first clock signal and a second clock signal. The memory controller transmits or receives a data signal. The first memory device receives the first clock signal and the second clock signal. The second memory device receives the first dock signal and the second clock signal. If a first mode register of the first memory device is in a first single-ended mode and a second mode register of the second memory device is in a second single-ended mode, the first memory device transmits or receives the data signal according to the first dock signal, and the second memory device transmits or receives the data signal according to the second clock signal.Type: ApplicationFiled: March 26, 2018Publication date: October 11, 2018Inventors: Bo-Wei HSIEH, Chia-Yu CHAN, Shang-Pin CHEN
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Patent number: 10083728Abstract: A memory module, comprising: a first pin, arranged to receive a first signal; a second pin, arranged to receive a second signal; a first conducting path, having a first end coupled to the first pin; at least one memory chip, coupled to the first conducting path for receiving the first signal; a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second to a second terminal of the predetermined resistor; wherein the first signal and the second are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed.Type: GrantFiled: July 6, 2014Date of Patent: September 25, 2018Assignee: MediaTek Inc.Inventors: Yan-Bin Luo, Sheng-Ming Chang, Bo-Wei Hsieh, Ming-Shi Liou, Chih-Chien Hung, Shang-Pin Chen