Patents by Inventor Boyd S. Phelps

Boyd S. Phelps has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Overriding a static prediction with a level-two predictor
    Patent number: 7533252
    Abstract: In one embodiment, the present invention includes a method for determining if an entry corresponding to a prediction address is present in a first predictor, and overriding a prediction output from a second predictor corresponding to the prediction address if the entry is present in the first predictor. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: May 12, 2009
    Assignee: Intel Corporation
    Inventors: Mark C. Davis, Stephan Jourdan, Robert L. Hinton, Boyd S. Phelps
  • Memory array with staged output
    Patent number: 7349284
    Abstract: Embodiments of the present invention provide a method and system for staging the data output from an addressable memory location as a plurality of fields. In embodiments, each field of a data item that is stored at an address may be output during a different clock cycle. In further embodiments, the most time critical field may be output first.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: March 25, 2008
    Assignee: Intel Corporation
    Inventors: Stephan J. Jourdan, Boyd S. Phelps, Chris E. Yuker
  • Overriding a static prediction
    Publication number: 20080059779
    Abstract: In one embodiment, the present invention includes a method for determining if an entry corresponding to a prediction address is present in a first predictor, and overriding a prediction output from a second predictor corresponding to the prediction address if the entry is present in the first predictor. Other embodiments are described and claimed.
    Type: Application
    Filed: August 31, 2006
    Publication date: March 6, 2008
    Inventors: Mark C. Davis, Stephan Jourdan, Robert L. Hinton, Boyd S. Phelps
  • Memory array with staged output
    Patent number: 7002873
    Abstract: Embodiments of the present invention provide a method and system for staging the data output from an addressable memory location as a plurality of fields. In embodiments, each field of a data item that is stored at an address may be output during a different clock cycle. In further embodiments, the most time critical field may be output first.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: February 21, 2006
    Assignee: Intel Corporation
    Inventors: Stephan J. Jourdan, Boyd S. Phelps, Chris E. Yuker