Abstract: A speculative transfer mechanism transfers a source synchronous read request from a first clock domain to a second clock domain. The address portion having address information is transferred to the second clock domain in response to detecting a source synchronous address strobe latching signal. A pointer is generated in response to detecting the address strobe latching signal and passed into the second clock domain. In one embodiment, a pointer is retimed to be stable for a timing window for which a crossover of the address portion may be performed in the second clock domain. Request logic in the second clock domain generates a read command based on the address portion and the pointer.

Abstract: A system controller includes a memory controller and a host interface residing in different clock domains. There is a time delay between the time when the memory controller issues a read command to a memory and the data becoming present and available at the host interface. The memory controller generates an alarm message at or near the time that it issues the read command. The alarm message indicates to the host interface the time that the data is available for transfer to a host.

Abstract: Display data and video data are stored within a graphics processing unit to reduce power consumed by the computing device during video playback. Storing display data and video data within the GPU reduces power consumption, because bus transaction activity is reduced and the need to read data from a larger, common main memory is avoided.

Abstract: Display data and video data are stored within a graphics processing unit to reduce power consumed by the computing device during video playback. Storing display data and video data within the GPU reduces power consumption, because bus transaction activity is reduced and the need to read data from a larger, common main memory is avoided.

Abstract: A method and system for implementing a generalized system stutter are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of blocking a first request received from a first of a plurality of bus masters during a low power state of a computing device for as long as permissible by the timing requirements of the computing device, wherein the first request is capable of triggering the computing device to transition out of the low power state, and during an active state of the computing device, servicing the first request along with other pending requests from the rest of the plurality of bus masters before the computing device transitions back to the low power state.

Abstract: Memory component temperature information is used to implement a method for ODT (on die termination) thermal load management. A respective temperature of a plurality of memory components are accessed, and based on this temperature, an ODT cycle is directed to a first of the memory components to avoid imposing a thermal load from the ODT cycle on a second of the memory components.

Abstract: A processor generates Z-cull information for tiles and groups of tiles. In one embodiment the processor includes an on-chip cache to coalesce Z information for tiles to identify occluded tiles. In a coprocessor embodiment, the processor provides Z-culling information to a graphics processor.

Abstract: A method for providing an operating system access to devices, including enumerating hardware devices and virtualized devices, where resources associated with a first hardware device are divided into guest physical resources creating a software virtualized device, and multiple instances of resources associated with a second hardware device are advertised thereby creating a hardware virtualized device. First and second permission lists are generated that specify which operating systems are permitted to access the software virtualized device and the hardware virtualized device, respectively. First and second sets of virtual address maps are generated, where each set maps an address space associated with either the software virtualized device or the hardware virtualized device into an address space associated with each operating system included in the corresponding permission list.

Abstract: A method for providing a first processor access to a memory associated with a second processor. The method includes receiving a first address map from the first processor that includes an MMIO aperture for a NUMA device, receiving a second address map from a second processor that includes MMIO apertures for hardware devices that the second processor is configured to access, and generating a global address map by combining the first and second address maps. The method further includes receiving an access request transmitted from the first processor to the NUMA device, generating a memory access request based on the first access request and a translation table that maps a first address associated with the first access request into a second address associated with the memory associated with the second processor, and routing the memory access request to the memory based on the global address map.

Abstract: A system has a plurality of different clients. Each client generates a report signal indicative of a current latency tolerance associated with a performance state. A controller dynamically determines a power down level having a minimum power consumption capable of supporting the system latency of the configuration state of the clients.

Abstract: One embodiment of the invention sets forth a technique for compressing and storing display data and optionally compressing and storing cursor data in a memory that is local to a graphics processing unit to reduce the power consumed by a mobile computing device when refreshing the screen. Compressing the display data and optionally the cursor data also reduces the relative cost of the invention by reducing the size of the local memory relative to the size that would be necessary if the display data were stored locally in uncompressed form. Thus, the invention may improve mobile computing device battery life, while keeping additional costs low.

Abstract: Circuits, methods, and apparatus for multiplexing addresses and data at a memory interface such that multiple data widths are provided without the need to change a motherboard or other printed circuit board design. A specific embodiment of the present invention achieves this using a single integrated circuit design where the datapath width is selected using a bonding option, fuse, data input, or other selection mechanism. The specific embodiment supports both 64 and 128-bit datapaths, though other numbers of datapaths, and other datapath widths are supported by other embodiments.

Abstract: A data path controller, a computer device, an apparatus and a method are disclosed for integrating power management functions into a data path controller to manage power consumed by processors and peripheral devices. By embedding power management within the data path controller, the data path controller can advantageously modify its criteria in-situ so that it can adapt its power management actions in response to changes in processors and peripheral devices. In addition, the data path controller includes a power-managing interface that provides power-monitoring ports for monitoring and/or quantifying power consumption of various components. In one embodiment, the data path controller includes a power-monitoring interface for selectably monitoring power of a component.

Abstract: Memory component temperature information is used to implement a method for ODT (on die termination) thermal load management. A respective temperature of a plurality of memory components are accessed, and based on this temperature, an ODT cycle is directed to a first of the memory components to avoid imposing a thermal load from the ODT cycle on a second of the memory components.

Abstract: Memory component temperature information is used to implement a method for ODT (on die termination) thermal load management. A respective temperature of a plurality of memory components are accessed, and based on this temperature, an ODT cycle is directed to a first of the memory components to avoid imposing a thermal load from the ODT cycle on a second of the memory components.

Abstract: A data path controller, a computer device, an apparatus and a method are disclosed for integrating power management functions into a data path controller to manage power consumed by processors and peripheral devices. By embedding power management within the data path controller, the data path controller can advantageously modify its criteria in-situ so that it can adapt its power management actions in response to changes in processors and peripheral devices. In addition, the data path controller includes a power-managing interface that provides power-monitoring ports for monitoring and/or quantifying power consumption of various components. In one embodiment, the data path controller includes a power-monitoring interface for selectably monitoring power of a component.

Abstract: A system, apparatus, and method are disclosed for storing and prioritizing predictions to anticipate nonsequential accesses to a memory. In one embodiment, an exemplary apparatus is configured as a prefetcher for predicting accesses to a memory. The prefetcher includes a prediction generator configured to generate a prediction that is unpatternable to an address. Also, the prefetcher also can include a target cache coupled to the prediction generator to maintain the prediction in a manner that determines a priority for the prediction. In another embodiment, the prefetcher can also include a priority adjuster. The priority adjuster sets a priority for a prediction relative to other predictions. In some cases, the placement of the prediction is indicative of the priority relative to priorities for the other predictions. In yet another embodiment, the prediction generator uses the priority to determine that the prediction is to be generated before other predictions.

Abstract: A processor generates Z-cull information for tiles and groups of tiles. In one embodiment the processor includes an on-chip cache to coalesce Z information for tiles to identify occluded tiles. In a coprocessor embodiment, the processor provides Z-culling information to a graphics processor.

Abstract: A method and system for implementing a generalized system stutter are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of blocking a first request received from a first of a plurality of bus masters during a low power state of a computing device for as long as permissible by the timing requirements of the computing device, wherein the first request is capable of triggering the computing device to transition out of the low power state, and during an active state of the computing device, servicing the first request along with other pending requests from the rest of the plurality of bus masters before the computing device transitions back to the low power state.

Abstract: A system, apparatus, and method are disclosed for managing predictive accesses to memory. In one embodiment, an exemplary apparatus is configured as a prediction inventory that stores predictions in a number of queues. Each queue is configured to maintain predictions until a subset of the predictions is either issued to access a memory or filtered out as redundant. In another embodiment, an exemplary prefetcher predicts accesses to a memory. The prefetcher comprises a speculator for generating a number of predictions and a prediction inventory, which includes queues each configured to maintain a group of items. The group of items typically includes a triggering address that corresponds to the group. Each item of the group is of one type of prediction. Also, the prefetcher includes an inventory filter configured to compare the number of predictions against one of the queues having the either the same or different prediction type as the number of predictions.