Abstract: The present invention provides a method and apparatus for handling critical blocking of store-to-load forwarding. One embodiment of the method includes recording a load that matches an address of a store in a store queue before the store has valid data. The load is blocked because the store does not have valid data. The method also includes replaying the load in response to the store receiving valid data so that the valid data is forwarded from the store queue to the load.

Abstract: An apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment are described. The method includes disregarding a received load secure region instruction when a currently active load secure region operation is detected. Otherwise, a memory protection element is directed, in response to the received load secure region instruction, to form a secure memory environment. Once directed, unauthorized read/write access to one or more protected memory regions are prohibited. Finally, a cryptographic hash value of the one or more protected memory regions is stored within a digest information repository as a secure software identification value. Once stored, outside agents may request access to a digitally signed software identification value to establish security verification of secure software within the secure memory environment.

Abstract: A method of loading a particular block of instructions into the instruction cache (14) of a Harvard architecture data processor (10) involves repetitively mis-predicting a branch instruction in a loop. The branch instruction is conditioned upon an instruction whose execution is contrived to output a sequential fetch address. However, the instruction's result is not available until after the branch instruction begins executing. Therefore, the data processor speculatively executes or predicts the branch instruction. In this case, the branch instruction predicts that it will branch to the particular block of instructions. The data processor then loads the instructions into its instruction cache. Later, the data processor determines that it mis-predicted the branch instruction, returning to the loop for another iteration.

Abstract: A mask-programmable read only memory bit cell (16) has a pair of conductive elements for each conductive layer in the integrated device but the last layer (30 and 34, 38 and 42, 46 and 50) and single conductive element in the last layer (54). The first and second elements in the first pair of elements receive a first and a second voltage supply (V.sub.DD and V.sub.GND), respectively. The single element outputs a voltage corresponding to the logic state stored by the bit cell. A plurality of pairs of conductive vias couple particular ones of the elements in each layer to particular ones of the elements in adjacent layers. The logic state stored by the bit cell may be reversed by reversing the connection of any one pair of elements and its associated vias. This makes the bit cell suitable for use in a processor version register.