Patents by Inventor Bradley Donald Bingham
Bradley Donald Bingham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11853195Abstract: A method, computer program product, and/or system is disclosed for identifying special cases for testing an integrated circuit that includes defining interesting cases, preferably by a user; obtaining an instruction from an instruction set architecture (ISA); determining that there is an interesting case for the obtained instruction; computing (i) a size of the input space (I0) of the ISA, and (ii) an interesting case space (Ii) which is an input space leading to the interesting case for the obtained instruction; obtaining a special case fraction by dividing the interesting case space (Ii) by the input space (I0); determining a special case fraction (Ii)/(I0) is less than a threshold; and identifying, in response to the special case fraction being less than the threshold, the interesting case as a special case. In an approach the special case is documented.Type: GrantFiled: September 13, 2021Date of Patent: December 26, 2023Assignee: International Business Machines CorporationInventors: Gregory A. Kemp, Bryant Cockcroft, Debapriya Chatterjee, Bradley Donald Bingham
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Patent number: 11740872Abstract: A method, a computer system, and a computer program product for detection of unintended dependencies between hardware design signals from pseudo-random number generator (PRNG) taps is provided. Embodiments of the present invention may include identifying one or more tap points in a design as an execution sequence. Embodiments of the present invention may include sampling the tap points by propagating the tap points in the design with different delays. Embodiments of the present invention may include defining observation points to identify tap collisions based on the tap points. Embodiments of the present invention may include identifying tap collisions. Embodiments of the present invention may include identifying one or more sources of the tap collisions in the design. Embodiments of the present invention may include eliminating the one or more sources of uninteresting tap collisions out of the tap collisions and filtering one or more of the tap collisions.Type: GrantFiled: September 29, 2020Date of Patent: August 29, 2023Assignee: International Business Machines CorporationInventors: Bradley Donald Bingham, Jason Raymond Baumgartner, Viresh Paruthi, Praveen S. Reddy
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Converting formal verification testbench drivers with nondeterministic inputs to simulation monitors
Patent number: 11675009Abstract: Techniques include configuring a sequential circuit monitor having been generated by applying a quantifier elimination to each random bit position of random inputs associated with a formal verification driver and selecting a value for random inputs to drive a next stage logic of sequential circuit simulation monitor, a state of the next stage logic being used by sequential circuit simulation monitor to generate sequential inputs to match those permitted by formal verification driver, formal verification driver being specified for a DUT input interface. An equivalence check between sequential circuit simulation monitor and original formal driver matches the same set of sequential inputs permitted original formal driver.Type: GrantFiled: August 10, 2021Date of Patent: June 13, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bradley Donald Bingham, Viresh Paruthi -
Publication number: 20230084275Abstract: A method, computer program product, and/or system is disclosed for identifying special cases for testing an integrated circuit that includes defining interesting cases, preferably by a user; obtaining an instruction from an instruction set architecture (ISA); determining that there is an interesting case for the obtained instruction; computing (i) a size of the input space (I0) of the ISA, and (ii) an interesting case space (Ii) which is an input space leading to the interesting case for the obtained instruction; obtaining a special case fraction by dividing the interesting case space (Ii) by the input space (I0); determining a special case fraction (Ii)/(I0) is less than a threshold; and identifying, in response to the special case fraction being less than the threshold, the interesting case as a special case. In an approach the special case is documented.Type: ApplicationFiled: September 13, 2021Publication date: March 16, 2023Inventors: Gregory A. Kemp, BRYANT COCKCROFT, DEBAPRIYA CHATTERJEE, BRADLEY Donald BINGHAM
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Publication number: 20230068740Abstract: A computer chip, a method, and computer program product for providing phase reservations between processing nodes. A computer chip includes a plurality of processing nodes interconnected in an on-chip data transfer network configured in a circular topology. The processing nodes include reservation mechanisms managing reservations made by processing nodes with phase constraints. The reservation policy allows the processing nodes to make a reservation, for a given phase, in any phase window, only once per reservation window. A reservation window can be a bounded amount of time for when a node is guaranteed an opportunity to transmit at least one message. The reservation policy also prevents the processing nodes from making more than one reservation in a phase window. Once a reservation is granted, the corresponding message may progress on the bus unimpeded. Requestors attempting to transmit messages are blocked until the message is transmitted.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Brendan M. Wong, Bradley Donald Bingham
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Publication number: 20230064969Abstract: A computer chip, a method, and computer program product for managing reservation between processing nodes with token constraints. The computer chip includes a plurality of processing nodes interconnected in an on-chip data transfer network configured in a circular topology. The processing nodes include a reservation mechanism that manages reservations made by the processing nodes. The reservation mechanism apply a reservation policy when a starvation condition is met on a processing node. The reservation policy separates the processing nodes into partition groups and dictates that a processing node may only send a reservation when their assigned partition group is active. Each of the processing nodes includes a buffer for storing messages that is divided into a pool of tokens and a pool of reservation tokens. The tokens are used for standard message transmission and the reservation tokens are reserved for token reservation requests received at a destination node.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Brendan M. WONG, Bradley Donald BINGHAM
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CONVERTING FORMAL VERIFICATION TESTBENCH DRIVERS WITH NONDETERMINISTIC INPUTS TO SIMULATION MONITORS
Publication number: 20220187368Abstract: Techniques include configuring a sequential circuit monitor having been generated by applying a quantifier elimination to each random bit position of random inputs associated with a formal verification driver and selecting a value for random inputs to drive a next stage logic of sequential circuit simulation monitor, a state of the next stage logic being used by sequential circuit simulation monitor to generate sequential inputs to match those permitted by formal verification driver, formal verification driver being specified for a DUT input interface. An equivalence check between sequential circuit simulation monitor and original formal driver matches the same set of sequential inputs permitted original formal driver.Type: ApplicationFiled: August 10, 2021Publication date: June 16, 2022Inventors: Bradley Donald Bingham, Viresh Paruthi -
Publication number: 20220100474Abstract: A method, a computer system, and a computer program product for detection of unintended dependencies between hardware design signals from pseudo-random number generator (PRNG) taps is provided. Embodiments of the present invention may include identifying one or more tap points in a design as an execution sequence. Embodiments of the present invention may include sampling the tap points by propagating the tap points in the design with different delays. Embodiments of the present invention may include defining observation points to identify tap collisions based on the tap points. Embodiments of the present invention may include identifying tap collisions. Embodiments of the present invention may include identifying one or more sources of the tap collisions in the design. Embodiments of the present invention may include eliminating the one or more sources of uninteresting tap collisions out of the tap collisions and filtering one or more of the tap collisions.Type: ApplicationFiled: September 29, 2020Publication date: March 31, 2022Inventors: BRADLEY Donald BINGHAM, Jason Raymond Baumgartner, Viresh Paruthi, Praveen S. Reddy
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Patent number: 11200361Abstract: A method, system and computer program product for appending abstractions to a testbench used for verifying the design of an electronic circuit. According to an embodiment of the invention, a method comprises identifying a set L of one or more support properties l for a set P of one or more properties p for a given electronic circuit; computing a plurality of hardware signals s of the given electronic circuit; and creating a plurality of abstract signals ABS, including declaring a fresh abstract signal abs_s for each of the hardware signals s, and creating a fresh abstract signal abs_l for each of the support properties l of the set L; for each of the properties p of the set P, creating an abstract property version abs_p; and appending the abstract signals ABS and the abstract property abs_p to the testbench to form an appended testbench.Type: GrantFiled: September 3, 2020Date of Patent: December 14, 2021Assignee: International Business Machines CorporationInventors: Bradley Donald Bingham, Viresh Paruthi, Steven Mark German
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Converting formal verification testbench drivers with nondeterministic inputs to simulation monitors
Patent number: 11150298Abstract: Techniques include configuring a sequential circuit monitor having been generated by applying a quantifier elimination to each random bit position of random inputs associated with a formal verification driver and selecting a value for random inputs to drive a next stage logic of sequential circuit simulation monitor, a state of the next stage logic being used by sequential circuit simulation monitor to generate sequential inputs to match those permitted by formal verification driver, formal verification driver being specified for a DUT input interface. An equivalence check between sequential circuit simulation monitor and original formal driver matches the same set of sequential inputs permitted original formal driver.Type: GrantFiled: December 11, 2020Date of Patent: October 19, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bradley Donald Bingham, Viresh Paruthi -
Patent number: 10970444Abstract: A method and/or system is disclosed for pre-silicon verification of a first integrated circuit design modified to a second integrated circuit design to avoid a hit of property P where property P has a known counterexample. The method/system includes applying a first implication check in an equivalence testbench on the first integrated circuit and on the second integrated circuit to determine whether the second integrated circuit hits property P in the same way as the first integrated circuit hits property P. Additionally or alternatively applying a second implication check to determine whether the second integrated circuit hits property P at a different timestep than the first integrated circuit hits property P. Additionally or alternatively applying a third implication check to determine whether the second integrated circuit hits property P further along a path than the first integrated circuit hits property P.Type: GrantFiled: August 10, 2020Date of Patent: April 6, 2021Assignee: International Business Machines CorporationInventors: Bradley Donald Bingham, Viresh Paruthi, Abrar Polani