Abstract: Systems and methods are disclosed for transferring data between a memory system and a vector register file. For example, a system may include a vector pipeline including a vector physical register file; a load store unit; one or more pipeline stages configured to decode a vector memory instruction to obtain a macro-operation and dispatch the macro-operation to both the load store unit and the vector pipeline, and a baler circuitry, including a buffer with entries. The vector pipeline is configured to crack the macro-operation into multiple micro-operations. The baler circuitry is configured to implement the multiple micro-operations to transfer data between one or more selected entries of the buffer and respective registers of the vector physical register file. The load store unit is configured to implement the macro-operation to transfer data between one or more addresses in a memory system and the one or more selected entries of the buffer.

Abstract: Systems and methods are disclosed for transferring an operand between a vector pipeline and a scalar pipeline. For example, some methods may include transferring an operand from a scalar pipeline to a scalar-to-vector buffer responsive to the scalar pipeline executing a first micro-op, wherein the scalar-to-vector buffer includes an entry having a width equal to a width of a scalar register of the scalar pipeline and a data store configured to store an indication mapping the entry to the first micro-op; updating the data store to include the indication mapping the entry to the first micro-op; identifying, by the vector pipeline in response to execution of a second micro-op and in dependence on the indication mapping the entry to the first micro-op, the entry storing the operand; and transferring the operand from the entry in the scalar-to-vector buffer to the vector pipeline responsive to the vector pipeline executing the second micro-op.

Abstract: Prediction circuitry may generate a vector length prediction associated with a configuration instruction prior to completion of execution of the configuration instruction. The vector length prediction may indicate a number of data elements on which a vector instruction will operate. In some implementations, the prediction circuitry can generate the vector length prediction by detecting a repeating pattern of vector lengths associated with earlier executions of the configuration instruction. In some implementations, the prediction circuitry can generate the vector length prediction by detecting decrements of an application vector length by a constant value.

Abstract: A method and apparatus to utilize a fetching scheme for instructions in a processor to limit the expenditure of power caused by the speculative execution of branch instructions is provided. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes calculating a cumulative confidence measure based on one or more outstanding conditional branch instructions. The method also includes reducing prefetching operations in response to detecting that the cumulative confidence measure is below a first threshold level.

Abstract: Reconfiguring a register file using a rename table having a plurality of fields that indicate fracture information about a source register of an instruction for instructions which have narrow to wide dependencies.

Abstract: A method and apparatus for simultaneously canceling a dependent instruction and a nested dependent instruction when a cancel timer of a source of the dependent instruction and a cancel timer of a source of the nested dependent instruction expire and a producer instruction speculatively waking up the dependent instruction is canceled.

Abstract: A method and apparatus for register packing prior to register renaming in a microprocessor are provided. The method includes: receiving a plurality of micro operations (micro-ops) decoded from one or more instructions; packing a plurality of registers which are included in the micro-ops into a packed register structure including a plurality of packed registers based on a preset number of rename ports of a renamer through which the packed registers are read or written for register renaming; and sending the packed registers for register renaming.

Abstract: Reconfiguring a register file using a rename table having a plurality of fields that indicate fracture information about a source register of an instruction for instructions which have narrow to wide dependencies.

Abstract: A method and apparatus for simultaneously canceling a dependent instruction and a nested dependent instruction when a cancel timer of a source of the dependent instruction and a cancel timer of a source of the nested dependent instruction expire and a producer instruction speculatively waking up the dependent instruction is canceled.

Abstract: A method and apparatus for register packing prior to register renaming in a microprocessor are provided. The method includes: receiving a plurality of micro operations (micro-ops) decoded from one or more instructions; packing a plurality of registers which are included in the micro-ops into a packed register structure including a plurality of packed registers based on a preset number of rename ports of a renamer through which the packed registers are read or written for register renaming; and sending the packed registers for register renaming.

Abstract: A method and apparatus to utilize a fetching scheme for instructions in a processor to limit the expenditure of power caused by the speculative execution of branch instructions is provided. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes calculating a cumulative confidence measure based on one or more outstanding conditional branch instructions. The method also includes reducing prefetching operations in response to detecting that the cumulative confidence measure is below a first threshold level.