Abstract: A method for improving semiconductor yield by in-line repair of defects during manufacturing comprises inspecting dies on a wafer after a selected layer is formed on the dies, identifying defects in each of the dies, classifying the identified defects as killer or non-critical, for each killer defect determining an action to correct the defect, repairing the defect and returning the wafer to a next process step. Also disclosed is a method for determining an efficient repair process by dividing the die into a grid and using analysis of the grid to find a least invasive repair.

Abstract: A resistor formed on a material layer of a semiconductor integrated circuit and a method for forming the resistor. The resistor comprises a region of resistive material with a plurality of conductive contacts or plugs in electrical contact with and extending away from the resistive material. A first and a second interconnect line are formed overlying the plugs and in conductive contact with one or more of the plurality of plugs, such that a portion of the resistive material between the first and the second interconnect lines provides a desired resistance. According to a method of the present invention, the plurality of conductive contacts are formed using a first photolithographic mask and the first and the second interconnect lines are formed using a second photolithographic mask. The desired resistance is changed by modifying the first or the second mask such that one or more dimensions of a region of the resistive material between the first and the second interconnect lines is altered.

Abstract: A method and apparatus for identifying crystal defects in emitter-base junctions of NPN bipolar transistors uses a test structure having an NP junction that can be inspected using passive voltage contrast. The test structure eliminates the collector of the transistor and simulates only the emitter and base. Eliminating the collector removes an NP junction between collector and substrate of a wafer allowing charge to flow from the substrate to emitter if the emitter-base junction is defective since only one NP junction exists in the test structure. In one embodiment, the test structures are located between dies on a wafer and may be formed in groups of several thousand.