Abstract: A water conditioner valve configured for use with a tank in a water conditioning system, including a main housing a working portion disposed within the main housing and further including at least one valve chamber, and at least a portion of the working portion is mounted within the tank.

Abstract: A water conditioner valve configured for use with a tank in a water conditioning system, including a main housing a working portion disposed within the main housing and further including at least one valve chamber, and at least a portion of the working portion is mounted within the tank.

Abstract: A two-stage alarm (10) includes a clock generator (36). A memory device (28 and 30) for storing data is connected to the clock generator (36). A data display device (22) is connected to the memory device (28 and 30) for displaying stored data. An alarm is connected to the memory device (28 and 30) with a first stage and a second attenuated stage. An alarm control device (24) is connected to the alarm for controlling the alarm in the absence of an alarm event and for selecting the second attenuated stage during an alarm event. As a result, the user of the two-stage alarm (10) can acknowledge an alarm event only by selecting an attenuated, reduced, alarm stage for a period of time and then manipulate the alarm only in the absence of an alarm event.

Abstract: A method of producing plant products containing modified starch content, including higher ratios of amylose to amylopectin, increase in intermediate material, or amylopectin having fewer branches or altered branching pattern. Also provided are DNA constructs and transformed plant cells useful in that method. The preferred method uses isoamylase from a Flavobacterium sp., more preferably in combination with a gene encoding ADPglucose pyrophosphorylase. Also disclosed are the gene from Flavobacterium sp. and transformed bacterial and plant cells containing a derivative thereof.

Abstract: A data processing system is provided having a secondary cache for performing a deferred cache load. The data processing system has a pipelined integer unit which uses an instruction prefetch unit (IPU) to maintain a steady stream of instructions to the pipeline. The (IPU) issues prefetch requests to a cache controller on a cache half-line basis. In conjunction with the prefetch request, the IPU transfers a prefetch address to a cache address memory management unit (CAMMU), for translation into a corresponding physical address. The physical address is compared with the indexed entries in a primary cache, and compared with the physical address corresponding to the single cache line stored in the secondary cache. When a prefetch miss occurs in both the primary and the secondary cache, the cache controller issues a bus transfer request to retrieve the requested cache line from an external memory.

Abstract: A filter structure uses multiple discrete filter circuits which are cascaded to provide a multiple tap filter of programmable tap length. In one form, an FIR filter may be implemented wherein each circuit generates partial sum operands which must be added to provide a filter output. The cascaded circuits perform partial addition operations near simultaneously by using a serial addition which is synchronized with a start bit. The number of taps in the filter structure implemented by the cascaded discrete filter circuits is variable and may be programmed with a programmable storage register in each discrete circuit which stores operand data fixing the tap length of each discrete circuit. The multiple filter circuits provide a single filter structure with a large tap length and high sampling rate.