Abstract: Methods and compositions are disclosed for modifying a semiconductor interconnect layer to reduce migration problems while minimizing resistance increases induced by the modifications. One method features creating trenches in the interconnect layer and filling these trenches with compositions that are less susceptible to migration problems. The trenches may be filled using traditional vapor deposition methods, or electroplating, or alternately by using electroless plating methods. Ion implantation may also be used as another method in modifying the interconnect layer. The methods and compositions for modifying interconnect layers may also be limited to the via/interconnect interface for improved performance. A thin seed layer may also be placed on the semiconductor substrate prior to applying the interconnect layer. This seed layer may also incorporate similar dopant and alloying materials in the otherwise pure metal.

Abstract: Methods and compositions are disclosed for modifying a semiconductor interconnect layer to reduce migration problems while minimizing resistance increases induced by the modifications. One method features creating trenches in the interconnect layer and filling these trenches with compositions that are less susceptible to migration problems. The trenches may be filled using traditional vapor deposition methods, or electroplating, or alternately by using electroless plating methods. Ion implantation may also be used as another method in modifying the interconnect layer. The methods and compositions for modifying interconnect layers may also be limited to the via/interconnect interface for improved performance. A thin seed layer may also be placed on the semiconductor substrate prior to applying the interconnect layer. This seed layer may also incorporate similar dopant and alloying materials in the otherwise pure metal.

Abstract: The present invention relates to a test structure and a method for forming a test structure over a semiconductor substrate. The test structure comprises a plurality of patterned electrically conductive metal layers within a scribe line. The plurality of metal layers further comprises one or more lower metal layers comprising a plurality of split pads longitudinally spaced along the length of the scribe line, wherein a channel traversing the length of the scribe line is define. One or more top metal layers comprising a plurality of solid pads generally residing over the split pads defines a plurality of columns of pads. One or more conduits generally residing within the channel are associated with one or more lower metal layers and connect two or more split pads associated with the respective one or more lower metal layers, wherein a bow-tie lead is defined.

Abstract: Methods and compositions are disclosed for modifying a semiconductor interconnect layer to reduce migration problems while minimizing resistance increases induced by the modifications. One method features creating trenches in the interconnect layer and filling these trenches with compositions that are less susceptible to migration problems. The trenches may be filled using traditional vapor deposition methods, or electroplating, or alternately by using electroless plating methods. Ion implantation may also be used as another method in modifying the interconnect layer. The methods and compositions for modifying interconnect layers may also be limited to the via/interconnect interface for improved performance. A thin seed layer may also be placed on the semiconductor substrate prior to applying the interconnect layer. This seed layer may also incorporate similar dopant and alloying materials in the otherwise pure metal.

Abstract: The present invention relates to a fuse and a method for forming a fuse over a semiconductor substrate. The fuse comprises forming a first contact member and a second contact member over a respective first region and a second region of a patterned, electrically-conductive silicide layer, wherein the first contact member and the second contact member electrically contact the silicide layer, thereby defining a first interface and a second interface, respectively. A first contact area and a second contact area are associated with the respective first contact member and second contact member, wherein the first contact area is larger than the second contact area, thereby defining a fusible link at the second interface. According to one example, the silicide resides over a patterned polysilicon layer, wherein the patterned polysilicon layer generally tapered, and wherein the first region is wider than the second region.