Abstract: A data transport module includes a connector to be received and coupled to a backplane within a modular platform. The data transport module also includes another connector to be received and coupled in a slot resident on a board such that the data transport module is coplanar to the board when received and coupled in the slot. The data transport module further includes one or more data transport interfaces to forward data between the board and the backplane via the connectors.

Abstract: An arbitration system for a shared address, data and control bus provides burst mode operations for transferring data between a peripheral device and memory via a bus master. The arbitration system is responsive to high priority bus activities, such as memory refresh cycles and DMA cycles to temporarily transfer control of the shared bus from the bus master to a circuit controlling the high priority activity. After the high priority activity is completed, the arbitration system returns control of the shared bus to the bus master so that the associated peripheral device may continue operating in the burst mode. This transfer of control occurs without requiring the time overhead of arbitrating priority between bus masters having active bus requests. The arbitration system further includes timing circuits to assure that a bus master transferring data in the burst mode does not retain control of the shared bus for an excessive amount of time.

Abstract: An arbitration system for a shared address, data and control bus provides burst mode operations for transferring data between a peripheral device and memory via a bus master. The arbitration system is responsive to high priority bus activities, such as memory refresh cycles and DMA cycles to temporarily transfer control of the shared bus from the bus master to a circuit controlling the high priority activity. After the high priority activity is completed, the arbitration system returns control of the shared bus to the bus master so that the associated peripheral device may continue operating in the burst mode. This transfer of control occurs without requiring the time overhead of arbitrating priority between bus masters having active bus requests. The arbitration system further includes timing circuits to assure that a bus master transferring data in the burst mode does not retain control of the shared bus for an excessive amount of time.