Abstract: A computer graphics system includes an apparatus for fog blending colors to be displayed on a graphics display of the computer graphics system. The computer graphics system includes a rendering parameter calculation unit responsive to data of a primitive, that determines a cooked exponent value and a color value for at least one pixel of the primitive. In addition, the system includes a fog unit responsive to the cooked exponent value for each pixel of the primitive, that determines a fog blending factor for each pixel of the primitive, wherein the fog blending factor is one of an exponential fog blending factor and an exponential-squared fog blending factor.

Abstract: Data values representative of a source image are processed with a dither matrix having dither values corresponding to pixel locations in the source image. The dither matrix has dimensions n.times.n, where n is modulo 4 and an integer value m exists such that m.multidot.m=n. The dither matrix is typically a 4.times.4 matrix. The dither values are arranged in the dither matrix such that each row, column, diagonal and m.times.m submatrix in the dither matrix adds to substantially the same value, preferably the sum of all dither values in the dither matrix divided by n. A dither value corresponding to a pixel location is accessed in the dither matrix. An initial data value associated with the pixel location is combined with the accessed dither value, typically by adding, to provide an intermediate value. The intermediate value is clamped and truncated to provide a dithered data value.

Abstract: A dot clock generation system has a voltage-controlled oscillator (VCO) for generating a dot clock signal for an analog-to-digital convertor (ADC). A dot clock synchronization (sync) generator counts cycles of the dot clock signal and generates a dot clock sync signal. An analog video signal is passed through a first differential buffer to create an analog video sync signal. The analog video sync signal is passed through a first flip-flop storage element to a phase detector. The dot clock sync signal is passed through a second storage element and then through a second differential buffer to the phase detector. The second storage buffer insures that the edge of the dot clock sync signal which is used by the phase detector is tightly tied with the sampling edge of the dot clock signal which is used by the ADC to sample the analog data within the analog video signal.

Abstract: A synchronization (sync) separation system and method quickly and accurately generate a sync signal from an analog video signal by using feedback control. The system comprises a voltage generator for generating first and second reference voltages V.sub.REF1, V.sub.REF2. A first comparator compares the analog video signal to the first reference voltage V.sub.REF1 and generates a shift control signal, A voltage shift mechanism receives the shift control signal and adjusts the analog video signal so that the sync level of the analog video signal converges toward the first reference voltage V.sub.REF1. A second comparator compares the analog video signal with the second reference voltage V.sub.REF2 and generates the sync signal indicative of when the analog video signal exhibits the sync level. Preferably, the voltage shift mechanism introduces a continuous current i.sub.c into the analog video signal.

Abstract: A frame rate conversion system synchronizes data transfers to and from a VRAM frame buffer which are concurrent, continuous, and asynchronous. The system comprises a frame buffer having a split memory for communicating data to a split output shift register. A frame buffer control supervises writing operations to the split memory at a first frame rate. A display control supervises reading operations from the shift register at a second frame rate which is slower than the first frame rate. The frame buffer control and the display control communicate control signals through double synchronizers. The display control has a counter for counting frames of data which have been read from the VRAM frame buffer. The display control prevents the writing of a frame into the split memory after a particular number of frames has been counted so as to prevent the frame buffer control from writing over and destroying existing data which has not yet been read from the split memory by the display control.