Abstract: A semiconductor device assembly includes a die stack, a plurality of thermoset regions, and underfill material. The die stack includes at least first and second dies that each have a plurality of conductive interconnect elements on upper surfaces. A portion of the interconnect elements are connected to through-silicon vias that extend between the upper surfaces and lower surfaces of the associated dies. The plurality of thermoset regions each comprise a thin layer of thermoset material extending from the lower surface of the second die to the upper surface of the first die, and are laterally-spaced and discrete from each other. Each of the thermoset regions extends to fill an area between a plurality of adjacent interconnect elements of the first die. The underfill material fills remaining open areas between the interconnect elements of the first die.

Abstract: Semiconductor devices having electrical interconnections through vertically stacked semiconductor dies, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor assembly includes a die stack having a plurality of semiconductor dies. Each semiconductor die can include surfaces having an insulating material, a recess formed in at least one surface, and a conductive pad within the recess. The semiconductor dies can be directly coupled to each other via the insulating material. The semiconductor assembly can further include an interconnect structure electrically coupled to each of the semiconductor dies. The interconnect structure can include a monolithic via extending continuously through each of the semiconductor dies in the die stack. The interconnect structure can also include a plurality of protrusions extending from the monolithic via.

Abstract: A bond tip for thermocompression bonding a bottom surface includes a die contact area and a low surface energy material covering at least a portion of the bottom surface. The low surface energy material may cover substantially all of the bottom surface, or only a peripheral portion surrounding the die contact area. The die contact area may be recessed with respect to the peripheral portion a depth at least as great as a thickness of a semiconductor die to be received in the recessed die contact area. A method of thermocompression bonding is also disclosed.

Abstract: A semiconductor device assembly that includes a semiconductor device positioned over a substrate with a number of electrical interconnections formed between the semiconductor device and the substrate. The surface of the substrate includes a plurality of discrete solder mask standoffs that extend towards the semiconductor device. A thermal compression bonding process is used to melt solder to form the electrical interconnects, which lowers the semiconductor device to contact and be supported by the plurality of discrete solder mask standoffs. The solder mask standoffs permit the application of a higher pressure during the bonding process than using traditional solder masks. The solder mask standoffs may have various polygonal or non-polygonal shapes and may be positioned in pattern to protect sensitive areas of the semiconductor device and/or the substrate. The solder mask standoffs may be an elongated shape that protects areas of the semiconductor device and/or substrate.

Abstract: Semiconductor devices having recessed edges with plated structures, semiconductor assemblies formed therefrom, and associated systems and methods are disclosed herein. In one embodiment, a semiconductor assembly includes a first semiconductor device and a second semiconductor device. The first semiconductor device can include an upper surface and a first dielectric layer over the upper surface, the second semiconductor device can include a lower surface and a second dielectric layer over the lower surface, and the first and second dielectric layers can be bonded to couple the first and second semiconductor devices. The first and second dielectric layers can each include a plurality of inwardly extending recesses exposing a plurality of metal structures on the respective upper and lower surfaces, and the upper surface recesses and metal structures can correspond to the lower surface recesses and metal structures. The metal structures can be electrically coupled by plated structures positioned in the recesses.

Abstract: This application relates to a method of processing microelectronic components comprising measuring parameter values of at least one of a nature and a degree of warpage of singulated microelectronic components in an unconstrained state and sorting the singulated microelectronic components responsive to the measured parameter values of at least one of the nature and degree of warpage. The sorted dice may be used in assemblies to minimize bond line height variances and resulting open circuits between components. Systems for implementing the methods are also disclosed.

Abstract: This patent application relates to methods and apparatus for temperature modification and reduction of contamination in bonding stacked microelectronic devices with heat applied from a bond head of a thermocompression bonding tool. The stack is substantially enclosed within a skirt carried by the bond head to reduce heat loss and contaminants from the stack, and heat may be added from the skirt.

Abstract: This patent application relates to methods and apparatus for temperature modification within a stack of microelectronic devices for mutual collective bonding of the microelectronic devices, and to related substrates and assemblies.

Abstract: Encapsulation warpage reduction for semiconductor die assemblies, and associated methods and systems are disclosed. In one embodiment, a semiconductor die assembly includes an interface die, a stack of semiconductor dies attached to a surface of the interface die, where the stack of semiconductor dies has a first height from the surface. The semiconductor die assembly also includes an encapsulant over the surface and surrounding the stack of semiconductor dies, where the encapsulant includes a sidewall with a first portion extending from the surface to a second height less than the first height and a second portion extending from the second height to the first height. Further, the first portion has a first texture and the second portion has a second texture different from the first texture.

Abstract: Semiconductor devices having recessed edges with plated structures, semiconductor assemblies formed therefrom, and associated systems and methods are disclosed herein. In one embodiment, a semiconductor assembly includes a first semiconductor device and a second semiconductor device. The first semiconductor device can include an upper surface and a first dielectric layer over the upper surface, the second semiconductor device can include a lower surface and a second dielectric layer over the lower surface, and the first and second dielectric layers can be bonded to couple the first and second semiconductor devices. The first and second dielectric layers can each include a plurality of inwardly extending recesses exposing a plurality of metal structures on the respective upper and lower surfaces, and the upper surface recesses and metal structures can correspond to the lower surface recesses and metal structures. The metal structures can be electrically coupled by plated structures positioned in the recesses.

Abstract: Semiconductor devices having electrical interconnections through vertically stacked semiconductor dies, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor assembly includes a die stack having a plurality of semiconductor dies. Each semiconductor die can include surfaces having an insulating material, a recess formed in at least one surface, and a conductive pad within the recess. The semiconductor dies can be directly coupled to each other via the insulating material. The semiconductor assembly can further include an interconnect structure electrically coupled to each of the semiconductor dies. The interconnect structure can include a monolithic via extending continuously through each of the semiconductor dies in the die stack. The interconnect structure can also include a plurality of protrusions extending from the monolithic via.

Abstract: A microelectronic device may have side surfaces each including a first portion and a second portion. The first portion may have a highly irregular surface topography extending from an adjacent surface of the microelectronic device. The second portion may have a less uneven surface extending from the first portion to an opposing surface of the microelectronic device. Methods of forming the microelectronic device may include creating dislocations in the wafer in a street between the one or more microelectronic devices by implanting ions and cleaving the wafer responsive to failure of stress concentrations near the dislocations through application of heat, tensile forces or a combination thereof. Related packages and methods are also disclosed.

Abstract: Microelectronic devices may include an active surface and a side surface. The side surface may include a first portion having a reflective surface and a second portion having a non-reflective surface. The reflective surface may be formed by depositing a conductive material in trenches formed in material of the wafer along streets between the microelectronic devices on a wafer. The conductive material may be heated. The wafer may be cooled after the conductive material is heated fracturing the wafer along the streets and separating the microelectronic devices.

Abstract: Semiconductor dies with edges protected and methods for generating the semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, trenches are formed on a front side of a substrate including semiconductor dies. Individual trenches correspond to scribe lines of the substrate where each trench has a depth greater than a final thickness of the semiconductor dies. A composite layer may be formed on sidewalls of the trenches to protect the edges of the semiconductor dies. The composite layer includes a metallic layer that shields the semiconductor dies from electromagnetic interference. Subsequently, the substrate may be thinned from a back side to singulate individual semiconductor dies from the substrate.

Abstract: Systems and methods for controlling contamination during thermocompression bonding are provided herein. The tool generally includes a bondhead having a first channel extending in a lateral direction from a first port along a second side toward a perimeter of the bondhead. In several examples, the bondhead includes a second channel fluidly coupled to a second port and extending in a lateral direction along an inset surface of the bondhead, where the second channel at least partially surrounds the first channel. In other examples, the tool includes a vacuum manifold having a vacuum opening positioned laterally outward from the bondhead. A first flow unit is coupled to the first channel and is configured to withdraw air. A second flow unit is coupled to the second port or the manifold to withdraw fluid and prevent outgassing bonding materials from entering the first channel, depositing on the bondhead, and/or contaminating neighboring semiconductor components.

Abstract: This patent application relates to methods and apparatus for temperature modification within a stack of microelectronic devices for mutual collective bonding of the microelectronic devices, and to related substrates and assemblies.

Abstract: Systems and methods for controlling contamination during thermocompression bonding are provided herein. The tool generally includes a bondhead having a first channel extending in a lateral direction from a first port along a second side toward a perimeter of the bondhead. In several examples, the bondhead includes a second channel fluidly coupled to a second port and extending in a lateral direction along an inset surface of the bondhead, where the second channel at least partially surrounds the first channel. In other examples, the tool includes a vacuum manifold having a vacuum opening positioned laterally outward from the bondhead. A first flow unit is coupled to the first channel and is configured to withdraw air. A second flow unit is coupled to the second port or the manifold to withdraw fluid and prevent outgas sing bonding materials from entering the first channel, depositing on the bondhead, and/or contaminating neighboring semiconductor components.

Abstract: Disclosed are methods and apparatus for protecting dielectric films on microelectronic components from contamination associated with singulation, picking and handling of singulated microelectronic components from a wafer for assembly with other components.

Abstract: This patent application relates to apparatus and methods for enhanced microelectronic device handling. Apparatus comprises a pick arm having a pick surface configured for receiving a microelectronic device thereon, drives for moving the pick arm and reorienting the pick surface in the X, Y and Z planes and about a horizontal rotational axis and a vertical rotational axis, and a sensor device carried by the pick arm and configured to detect at least one of at least one magnitude of force and at least one location of force applied between the pick surface and a structure contacted by the pick surface or a structure and a microelectronic device carried on the pick surface. Related methods are also disclosed.

Abstract: Methods for protecting edges of semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, a plurality of trenches may be formed on a front side of a substrate including a plurality of semiconductor dies. Individual trenches may correspond to scribe lines of the substrate where each trench includes a depth greater than a final thickness of the semiconductor dies. A dielectric layer may be formed on sidewalls of the trenches, thereby protecting the edges of the semiconductor dies, prior to filling the trenches with an adhesive material. Subsequently, the substrate may be thinned from a back side such that the adhesive material in the trenches may be exposed from the back side. The adhesive material may be removed to singulate individual semiconductor dies of the plurality from the substrate.