Abstract: Apparatus and methods are provided for overload recovery in high order sigma-delta feedback topologies. An apparatus is provided for an analog-to-digital converter. The analog-to-digital converter comprises a first integrator having a first input, wherein the first integrator is configured to produce a first integrated output. A first switched resistance element is coupled between the first input and the first integrated output, wherein the first integrated output is altered when the first switched resistance element is activated. A quantizer is coupled to the first integrated output, the quantizer having a digital output wherein the quantizer converts the first integrated output to a digital value. A digital-to-analog converter is coupled between the digital output and the first input, wherein the digital-to-analog converter converts the digital value to an analog value.

Abstract: Apparatus and methods are provided for overload recovery in high order sigma-delta feedback topologies. An apparatus is provided for an analog-to-digital converter. The analog-to-digital converter comprises a first integrator having a first input, wherein the first integrator is configured to produce a first integrated output. A first switched resistance element is coupled between the first input and the first integrated output, wherein the first integrated output is altered when the first switched resistance element is activated. A quantizer is coupled to the first integrated output, the quantizer having a digital output wherein the quantizer converts the first integrated output to a digital value. A digital-to-analog converter is coupled between the digital output and the first input, wherein the digital-to-analog converter converts the digital value to an analog value.

Abstract: A double sampled switched capacitor architecture as described herein includes an amplifier having two separate inputs corresponding to two separate amplifier sections. The amplifier uses a first differential transistor pair for the first amplifier section, a second differential transistor pair for the second amplifier section, a first tail current bias arrangement for the first differential transistor pair, and a second tail current bias arrangement for the second differential transistor pair. The tail current bias arrangements are driven by a bias switching architecture that alternately activates one tail current bias arrangement while at least partially deactivating the other tail current bias arrangement. The amplifier and bias switching architecture cooperate to eliminate gain error that would otherwise be caused by a common parasitic capacitance shared by a single amplifier section.

Abstract: A double sampled switched capacitor architecture as described herein includes an amplifier having two separate inputs corresponding to two separate amplifier sections. The amplifier uses a first differential transistor pair for the first amplifier section, a second differential transistor pair for the second amplifier section, a first tail current bias arrangement for the first differential transistor pair, and a second tail current bias arrangement for the second differential transistor pair. The tail current bias arrangements are driven by a bias switching architecture that alternately activates one tail current bias arrangement while at least partially deactivating the other tail current bias arrangement. The amplifier and bias switching architecture cooperate to eliminate gain error that would otherwise be caused by a common parasitic capacitance shared by a single amplifier section.

Abstract: A double sampled switched capacitor architecture as described herein includes an amplifier having two separate inputs corresponding to two separate amplifier sections. The amplifier uses a first differential transistor pair for the first amplifier section, a second differential transistor pair for the second amplifier section, a first tail current bias arrangement for the first differential transistor pair, and a second tail current bias arrangement for the second differential transistor pair. The tail current bias arrangements are driven by a bias switching architecture that alternately activates one tail current bias arrangement while at least partially deactivating the other tail current bias arrangement. The amplifier and bias switching architecture cooperate to eliminate gain error that would otherwise be caused by a common parasitic capacitance shared by a single amplifier section.

Abstract: Methods and corresponding systems for calibrating a digital-to-analog converter include selecting first and second code regions in the digital-to-analog converter, wherein the first and second code regions are separated by a boundary. Thereafter a waveform sequence is input into the digital-to-analog converter, wherein the waveform sequence has a zero offset at the boundary. Then a relative compensation value between the first and second code regions is adjusted to reduce a distortion in an output of the digital-to-analog converter. A magnitude of a third harmonic distortion of the waveform sequence can be used to measure distortion in the output. Adjusting the relative compensation can include converting the output of the digital-to-analog converter to a digital sequence, filtering the digital sequence, and measuring a harmonic distortion in the digital sequence.

Abstract: Methods and corresponding systems for calibrating a digital-to-analog converter include selecting first and second code regions in the digital-to-analog converter, wherein the first and second code regions are separated by a boundary. Thereafter a waveform sequence is input into the digital-to-analog converter, wherein the waveform sequence has a zero offset at the boundary. Then a relative compensation value between the first and second code regions is adjusted to reduce a distortion in an output of the digital-to-analog converter. A magnitude of a third harmonic distortion of the waveform sequence can be used to measure distortion in the output. Adjusting the relative compensation can include converting the output of the digital-to-analog converter to a digital sequence, filtering the digital sequence, and measuring a harmonic distortion in the digital sequence.

Abstract: A switched-capacitor gain stage suitable for use with a pipelined analog to digital converter (“ADC”) is capable of processing two or more input channels. The analog input voltages from the multiple channels are concurrently sampled (every other clock phase), and the gain stage processes the samples using a double sampling technique, generates residual voltage samples (every clock phase), and generates digital outputs for the multiple channels in an alternating manner. The gain stage provides equal input loading for the input stages, which enhances the performance of the ADC.

Abstract: A system and method for converting an analog signal to a digital signal is provided including a first circuit (22) having a signal range and an input for receiving a first signal, and a second circuit (24) having an input receiving the analog signal and a first output coupled to the input of the first circuit. The first circuit (22) includes an amplifier (28). The first circuit (22) samples the first signal and produces the digital signal from the first signal using the amplifier. A second output of the second circuit (24) is coupled to the amplifier (28). The second circuit (24) samples and scales the analog signal via the amplifier (28) to produce the first signal within the signal range and cancels an offset of the first signal. The system and method reduce power consumption and save device area.

Abstract: A system and method for converting an analog signal to a digital signal is provided including a first circuit (22) having a signal range and an input for receiving a first signal, and a second circuit (24) having an input receiving the analog signal and a first output coupled to the input of the first circuit. The first circuit (22) includes an amplifier (28). The first circuit (22) samples the first signal and produces the digital signal from the first signal using the amplifier. A second output of the second circuit (24) is coupled to the amplifier (28). The second circuit (24) samples and scales the analog signal via the amplifier (28) to produce the first signal within the signal range and cancels an offset of the first signal. The system and method reduce power consumption and save device area.

Abstract: Apparatus for sensing a current across a known resistor comprising a switched capacitor network and an amplifier having an input coupled to an output of the switched capacitor network. The switched capacitor network is configured to sample first and second reference potentials indicating the current. The amplifier is configured to produce first and second amplified potentials at an output of the amplifier based on the first and second reference potentials.

Abstract: A light modulation system as described herein can be incorporated into a personal or portable electronic apparatus such as a cellular telephone, a digital music player, or the like. The light modulation system controls the activation of light elements, such as light emitting diodes, of the host electronic apparatus in response to one or more analog audio signals available at the host electronic apparatus. The analog audio signals may be obtained from any suitable analog audio path or source in the host electronic apparatus. The light modulation system is compact, inexpensive to implement, and need not rely on digital signal processors for operation.

Abstract: A double sampled switched capacitor architecture as described herein includes an amplifier having two separate inputs corresponding to two separate amplifier sections. The amplifier uses a first differential transistor pair for the first amplifier section, a second differential transistor pair for the second amplifier section, a first tail current bias arrangement for the first differential transistor pair, and a second tail current bias arrangement for the second differential transistor pair. The tail current bias arrangements are driven by a bias switching architecture that alternately activates one tail current bias arrangement while at least partially deactivating the other tail current bias arrangement. The amplifier and bias switching architecture cooperate to eliminate gain error that would otherwise be caused by a common parasitic capacitance shared by a single amplifier section.

Abstract: A switched-capacitor gain stage suitable for use with a pipelined analog to digital converter (“ADC”) is capable of processing two or more input channels. The analog input voltages from the multiple channels are concurrently sampled (every other clock phase), and the gain stage processes the samples using a double sampling technique, generates residual voltage samples (every clock phase), and generates digital outputs for the multiple channels in an alternating manner. The gain stage provides equal input loading for the input stages, which enhances the performance of the ADC.

Abstract: Apparatus for sensing a current across a known resistor comprising a switched capacitor network and an amplifier having an input coupled to an output of the switched capacitor network. The switched capacitor network is configured to sample first and second reference potentials indicating the current. The amplifier is configured to produce first and second amplified potentials at an output of the amplifier based on the first and second reference potentials.

Abstract: A light modulation system as described herein can be incorporated into a personal or portable electronic apparatus such as a cellular telephone, a digital music player, or the like. The light modulation system controls the activation of light elements, such as light emitting diodes, of the host electronic apparatus in response to one or more analog audio signals available at the host electronic apparatus. The analog audio signals may be obtained from any suitable analog audio path or source in the host electronic apparatus. The light modulation system is compact, inexpensive to implement, and need not rely on digital signal processors for operation.

Abstract: Apparatus for sensing a current across a known resistor including a switched capacitor network and an amplifier having an input coupled to an output of the switched capacitor network. The switched capacitor network is configured to sample first and second reference potentials indicating the current. The amplifier is configured to produce first and second amplified potentials at an output of the amplifier based on the first and second reference potentials.

Abstract: A pipelined analog to digital converter (“ADC”) as described herein is capable of processing two or more input channels. The analog input voltages from the multiple channels are concurrently sampled (every other clock phase) using isolated input stages. The outputs of the input stages are concurrently sampled (every other clock phase) by a delay/holding and synchronization (“DHS”) stage. The DHS stage processes the samples using a double sampling technique, generates residual voltage samples (every clock phase), and generates digital outputs for the multiple channels in an alternating manner. The DHS stage provides equal input loading for the input stages, which enhances the performance of the ADC.

Abstract: A method and apparatus are provided for reducing the size and power of cyclic analog-to-digital converter (ADC) conversion circuits. During each cycle, the ADC conversion circuit generates a plurality of bits. The improved ADC includes a scaling/reference circuit having a single operational amplifier which operates in a reference generation mode and an analog multiplexing mode during generation of the first bit and operates in the analog multiplexing mode during generation of the subsequent bits.