Abstract: A universal asynchronous receiver/transmitter (UART) interface is disclosed. The UART interface may include a configurable asynchronous receiver and transmitter unit; and a configurable state machine, wherein the state machine allows configuration of the receiver and transmitter unit to support various baud rates and provide for start bit and stop bit configuration, wherein the state machine is further configurable to automatically support a plurality of communication protocols.

Abstract: Systems and methods for a run-time error correction code (“ECC”) error injection scheme for hardware validation are disclosed. The systems and methods include configuring a read path to internally forward read data, and injecting at least one faulty bit into the forwarded read data via a read fault injection logic. The systems and methods may also include configuring a write path to internally forward write data, and injecting at least one faulty bit into the forwarded write data via a write fault injection logic.

Abstract: A central processing unit with dual boot capabilities is disclosed comprising an instruction memory further comprising a first and second memory area which are configured to be individually programmable, wherein first and second memory area can be assigned to an active memory from which instructions are executed and an inactive memory, respectively. The instruction set for the central processing unit comprises a dedicated instruction that allows to perform a swap from the an active memory area to an inactive memory area, wherein the swap is performed by executing the dedicated instruction in the active memory followed by a program flow change instruction in the active memory, whereupon the inactive memory becomes the new active memory and the active memory becomes the new inactive memory and execution of instructions continues in the new active memory.

Abstract: A universal asynchronous receiver/transmitter (UART) interface is disclosed. The UART interface may include a configurable asynchronous receiver and transmitter unit; and a configurable state machine, wherein the state machine allows configuration of the receiver and transmitter unit to support various baud rates and provide for start bit and stop bit configuration, wherein the state machine is further configurable to automatically support a plurality of communication protocols.

Abstract: Systems and methods for a run-time error correction code (“ECC”) error injection scheme for hardware validation are disclosed. The systems and methods include configuring a read path to internally forward read data, and injecting at least one faulty bit into the forwarded read data via a read fault injection logic. The systems and methods may also include configuring a write path to internally forward write data, and injecting at least one faulty bit into the forwarded write data via a write fault injection logic.

Abstract: A microcontroller has a timebase driven by a clock signal, wherein the timebase has a reset input and an output coupled with a comparator. The comparator is further coupled with a register and is operable to generate a synchronization output signal if the timebase matches the register value. The microcontroller further has a first multiplexer receiving the synchronization output signal from the comparator and further receiving at least one event signal generated by a unit other than the timebase, wherein the first multiplexer is operable to select either the synchronization output signal or the at least one event signal as a timebase synchronization output signal.

Abstract: A central processing unit with dual boot capabilities is disclosed comprising an instruction memory further comprising a first and second memory area which are configured to be individually programmable, wherein first and second memory area can be assigned to an active memory from which instructions are executed and an inactive memory, respectively. The instruction set for the central processing unit comprises a dedicated instruction that allows to perform a swap from the an active memory area to an inactive memory area, wherein the swap is performed by executing the dedicated instruction in the active memory followed by a program flow change instruction in the active memory, whereupon the inactive memory becomes the new active memory and the active memory becomes the new inactive memory and execution of instructions continues in the new active memory.

Abstract: A cyclic redundancy check (CRC) unit has a programmable CRC engine, a variable buffer memory operable to store k words wherein each word has n-bits, wherein k and n can be varied, and shift logic operable to shift data from the variable buffer memory into the programmable CRC engine.

Abstract: A cyclic redundancy check (CRC) unit has a programmable CRC engine, a variable buffer memory operable to store k words wherein each word comprises n-bits, wherein k and n can be varied, and shift logic operable to shift data from said FIFO memory into said programmable CRC engine.