Abstract: A computer chip, a method, and computer program product for managing reservation between processing nodes with token constraints. The computer chip includes a plurality of processing nodes interconnected in an on-chip data transfer network configured in a circular topology. The processing nodes include a reservation mechanism that manages reservations made by the processing nodes. The reservation mechanism apply a reservation policy when a starvation condition is met on a processing node. The reservation policy separates the processing nodes into partition groups and dictates that a processing node may only send a reservation when their assigned partition group is active. Each of the processing nodes includes a buffer for storing messages that is divided into a pool of tokens and a pool of reservation tokens. The tokens are used for standard message transmission and the reservation tokens are reserved for token reservation requests received at a destination node.

Abstract: A computer chip, a method, and computer program product for providing phase reservations between processing nodes. A computer chip includes a plurality of processing nodes interconnected in an on-chip data transfer network configured in a circular topology. The processing nodes include reservation mechanisms managing reservations made by processing nodes with phase constraints. The reservation policy allows the processing nodes to make a reservation, for a given phase, in any phase window, only once per reservation window. A reservation window can be a bounded amount of time for when a node is guaranteed an opportunity to transmit at least one message. The reservation policy also prevents the processing nodes from making more than one reservation in a phase window. Once a reservation is granted, the corresponding message may progress on the bus unimpeded. Requestors attempting to transmit messages are blocked until the message is transmitted.

Abstract: An apparatus, method, program product, and system are disclosed for evicting pages from memory using a neural network. One embodiment of a method for evicting pages from memory using a neural network includes determining state information related to evicting pages from memory. The state information may be determined by a dedicated hardware snooping device that snoops a system bus for the state information. The method includes determining an identifier for a page in memory to be evicted using a neural network. The neural network performs machine learning operations on the state information to identify the page in memory to be evicted. The method includes locating the identified page in memory using the identifier determined by the neural network and evicting the identified page from memory.

Abstract: An apparatus, method, program product, and system are disclosed for evicting pages from memory using a neural network. A state module determines state information related to evicting pages from memory. The state information may be determined by a dedicated hardware snooping device that snoops a system bus for the state information. A learning module determines an identifier for a page in memory to be evicted using a neural network. The neural network may perform machine learning operations on the state information to identify the page in memory to be evicted. An eviction module locates the identified page in memory using the identifier determined by the neural network and evicts the identified page from memory.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices. Operation of such a multi-slice processor includes: receiving a first instruction indicating a first target register; receiving a second instruction indicating the first target register as a source operand; responsive to the second instruction indicating the first target register as a source operand, updating a dependent count corresponding to the first instruction; and issuing, in dependence upon the dependent count for the first instruction being greater than a dependent count for another instruction, the first instruction to an execution slice of the plurality of execution slices.

Abstract: An apparatus, method, program product, and system are disclosed for evicting pages from memory using a neural network. A state module determines state information related to evicting pages from memory. The state information may be determined by a dedicated hardware snooping device that snoops a system bus for the state information. A learning module determines an identifier for a page in memory to be evicted using a neural network. The neural network may perform machine learning operations on the state information to identify the page in memory to be evicted. An eviction module locates the identified page in memory using the identifier determined by the neural network and evicts the identified page from memory.

Abstract: An apparatus, method, program product, and system are disclosed for evicting pages from memory using a neural network. One embodiment of a method for evicting pages from memory using a neural network includes determining state information related to evicting pages from memory. The state information may be determined by a dedicated hardware snooping device that snoops a system bus for the state information. The method includes determining an identifier for a page in memory to be evicted using a neural network. The neural network performs machine learning operations on the state information to identify the page in memory to be evicted. The method includes locating the identified page in memory using the identifier determined by the neural network and evicting the identified page from memory.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices, where the load/store slices are coupled to the execution slices via a results bus. Operation of such a multi-slice processor includes: capturing first state information corresponding to a first set of control signals; monitoring state information of a plurality of logical components of the multi-slice processor; selecting, in dependence upon one or more selection criteria and upon the monitored state information, a second set of control signals; and capturing second state information corresponding to the second set of control signals, wherein the first set of control signals is different than the second set of control signals.

Abstract: Systems, methods, and apparatuses to perform an operation comprising receiving an indication of a first error in a processor, identifying a first control signal, of a plurality of control signals in a debug bus, associated with the error, wherein each of the plurality of control signals are coupled to one of a plurality of input ports of a multiplexer, and changing a configuration state of the multiplexer to output the first control signal to a trace array.

Abstract: Operation of a computer processor that includes: receiving a first instruction indicating a first target register; receiving, from an instruction fetch unit of the computer processor, a first instruction and a branch instruction; responsive to determining that the branch instruction is dependent upon a result of the first instruction, updating a priority value corresponding to the first instruction; and issuing, in dependence upon the priority value for the first instruction having a higher priority than a priority value for another instruction, the first instruction to an execution unit of the computer processor.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices. Operation of such a multi-slice processor includes: receiving a first instruction indicating a first target register; receiving a second instruction indicating the first target register as a source operand; responsive to the second instruction indicating the first target register as a source operand, updating a dependent count corresponding to the first instruction; and issuing, in dependence upon the dependent count for the first instruction being greater than a dependent count for another instruction, the first instruction to an execution slice of the plurality of execution slices.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices, where the load/store slices are coupled to the execution slices via a results bus. Operation of such a multi-slice processor includes: capturing first state information corresponding to a first set of control signals; monitoring state information of a plurality of logical components of the multi-slice processor; selecting, in dependence upon one or more selection criteria and upon the monitored state information, a second set of control signals; and capturing second state information corresponding to the second set of control signals, wherein the first set of control signals is different than the second set of control signals.

Abstract: Systems, methods, and apparatuses to perform an operation comprising receiving an indication of a first error in a processor, identifying a first control signal, of a plurality of control signals in a debug bus, associated with the error, wherein each of the plurality of control signals are coupled to one of a plurality of input ports of a multiplexer, and changing a configuration state of the multiplexer to output the first control signal to a trace array.