Patents by Inventor Brendan T. Mangan

Brendan T. Mangan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MEMORY CONTROLLER WITH A PLURALITY OF COMMAND SUB-QUEUES AND CORRESPONDING ARBITERS
    Publication number: 20230031595
    Abstract: A memory controller includes a memory channel controller that uses multiple groups of command queue and arbiter pairs. Each arbiter is coupled to a respective command queue to select memory access commands from each command queue according to predetermined criteria. Each arbiter selects from among the memory access requests in each command queue independently based on the predetermined criteria and sends selected memory access requests to a selector that serves as a second level arbiter which sends the request to a memory subchannel.
    Type: Application
    Filed: October 7, 2022
    Publication date: February 2, 2023
    Inventors: JAMES R. MAGRO, KEDARNATH BALAKRISHNAN, BRENDAN T. MANGAN
  • Memory controller with a plurality of command sub-queues and corresponding arbiters
    Patent number: 11494316
    Abstract: A memory controller includes a memory channel controller that uses multiple groups of command queue and arbiter pairs. Each arbiter is coupled to a respective command queue to select memory access commands from each command queue according to predetermined criteria. Each arbiter selects from among the memory access requests in each command queue independently based on the predetermined criteria and sends selected memory access requests to a selector that serves as a second level arbiter which sends the request to a memory subchannel.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: November 8, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: James R. Magro, Kedarnath Balakrishnan, Brendan T. Mangan
  • MEMORY CONTROLLER WITH A PLURALITY OF COMMAND SUB-QUEUES AND CORRESPONDING ARBITERS
    Publication number: 20220058141
    Abstract: A memory controller includes a memory channel controller that uses multiple groups of command queue and arbiter pairs. Each arbiter is coupled to a respective command queue to select memory access commands from each command queue according to predetermined criteria. Each arbiter selects from among the memory access requests in each command queue independently based on the predetermined criteria and sends selected memory access requests to a selector that serves as a second level arbiter which sends the request to a memory subchannel.
    Type: Application
    Filed: October 30, 2020
    Publication date: February 24, 2022
    Inventors: James R. Magro, Kedarnath Balakrishnan, Brendan T. Mangan