Abstract: A method includes receiving radar parameters from a unit under test (UUT). The method also includes generating a simulated radar return for the UUT using at least one graphics processing unit (GPU), where the simulated radar return includes digital signals. The method further includes controlling a timing of output of the simulated radar return to the UUT using at least one field programmable gate array (FPGA) carrier. The method also includes converting the digital signals into analog signals using multiple digital-to-analog converters (DACs). In addition, the method includes transmitting the analog signals to the UUT.

Abstract: A method includes receiving, at a radar timing card, radar timing information and a synchronous clock signal. The method also includes generating, using the radar timing card, a timing trigger to indicate a time of transmission for radar return information. The method further includes receiving, at each of multiple digital-to-analog converter (DAC) channels of one or more DAC cards, the synchronous clock signal and the timing trigger. In addition, the method includes simultaneously transmitting, from each of the DAC channels, a dedicated portion of the radar return information based on the time of transmission indicated by the timing trigger. The synchronous clock signal is used to align the simultaneous transmissions of the DAC channels on the one or more DAC cards.

Abstract: A method includes receiving, at a radar timing card, radar timing information and a synchronous clock signal. The method also includes generating, using the radar timing card, a timing trigger to indicate a time of transmission for radar return information. The method further includes receiving, at each of multiple digital-to-analog converter (DAC) channels of one or more DAC cards, the synchronous clock signal and the timing trigger. In addition, the method includes simultaneously transmitting, from each of the DAC channels, a dedicated portion of the radar return information based on the time of transmission indicated by the timing trigger. The synchronous clock signal is used to align the simultaneous transmissions of the DAC channels on the one or more DAC cards.

Abstract: A method includes receiving radar parameters from a unit under test (UUT). The method also includes generating a simulated radar return for the UUT using at least one graphics processing unit (GPU), where the simulated radar return includes digital signals. The method further includes controlling a timing of output of the simulated radar return to the UUT using at least one field programmable gate array (FPGA) carrier. The method also includes converting the digital signals into analog signals using multiple digital-to-analog converters (DACs). In addition, the method includes transmitting the analog signals to the UUT.