Abstract: A power planning phase module, a placement phase module, and a routing phase module are provided that can replace, supplement, or enhance existing electronic design automation (EDA) software tools. The power planning phase module adds distributed power sources and a network of switching elements to the power frame or ring assigned to regions of a chip (that may be identified during a floor planning stage). The placement phase module optimizes a number and type of cells attached to each power source of the distributed power sources already added or to be added during the power planning phase. The routing phase module optimizes routing length to, for example, mask power consumption.

Abstract: To enable detection of a plurality of capsule ingestions, the ingestible capsules include a transmitter and processing hardware to generate and transmit the signals. Each ingestible capsule obtains a serial number for distinguishing between the ingestible capsules, and generates a signal indicating that the capsule has been ingested. The signal includes a series of pulses having a particular pulse space and indicating the serial number. Each ingestible capsule transmits the signal to a receiver via the transmitter, where each ingestible capsule is identified based on at least one of: the particular pulse space and the serial number for the ingestible capsule.

Abstract: Ingestible bio-telemetry communication network and associated systems are described. The communication network can include one or more ingestible bio-telemetry tags; and a reader, wherein each of the one or more ingestible bio-telemetry tags generates an out-link signal comprising, for each bit of data in a frame, a pulse reverse keyed symbol. Multiple ingestible bio-telemetry tags can be managed at the same time by allowing the frequency of the transmit carrier signal to change, or “hop” to different frequencies so as to minimize likelihood of collision. A reader can identify the proper frequency either by a signal from the tags indicated the frequency of the next hop or, when no bi-directional communication is available, by deducing the carrier signal frequency from the start bits of a received frame from the tag and scanning for the shifted carrier signal frequency within a tolerance of the deduced carrier signal frequency.

Abstract: A power planning phase module, a placement phase module, and a routing phase module are provided that can replace, supplement, or enhance existing electronic design automation (EDA) software tools. The power planning phase module adds distributed power sources and a network of switching elements to the power frame or ring assigned to regions of a chip (that may be identified during a floor planning stage). The placement phase module optimizes a number and type of cells attached to each power source of the distributed power sources already added or to be added during the power planning phase. The routing phase module optimizes routing length to, for example, mask power consumption.

Abstract: A power planning phase module, a placement phase module, and a routing phase module are provided that can replace, supplement, or enhance existing electronic design automation (EDA) software tools. The power planning phase module adds distributed power sources and a network of switching elements to the power frame or ring assigned to regions of a chip (that may be identified during a floor planning stage). The placement phase module optimizes a number and type of cells attached to each power source of the distributed power sources already added or to be added during the power planning phase. The routing phase module optimizes routing length to, for example, mask power consumption.

Abstract: Ingestible bio-telemetry communication network and associated systems are described. The communication network can include one or more ingestible bio-telemetry tags; and a reader, wherein each of the one or more ingestible bio-telemetry tags generates an out-link signal comprising, for each bit of data in a frame, a pulse reverse keyed symbol. Multiple ingestible bio-telemetry tags can be managed at the same time by allowing the frequency of the transmit carrier signal to change, or “hop” to different frequencies so as to minimize likelihood of collision. A reader can identify the proper frequency either by a signal from the tags indicated the frequency of the next hop or, when no bi-directional communication is available, by deducing the carrier signal frequency from the start bits of a received frame from the tag and scanning for the shifted carrier signal frequency within a tolerance of the deduced carrier signal frequency.

Abstract: An electronic drug compliance monitoring system and associated methods utilize a pill having an electronic transmission capability and external means for receiving that transmission to sense the presence of the pill in the patient's body or digestive tract.

Abstract: Ingestible bio-telemetry communication network and associated systems are described. The communication network can include one or more ingestible bio-telemetry tags; and a reader, wherein each of the one or more ingestible bio-telemetry tags generates an out-link signal comprising, for each bit of data in a frame, a pulse reverse keyed symbol. Multiple ingestible bio-telemetry tags can be managed at the same time by allowing the frequency of the transmit carrier signal to change, or “hop” to different frequencies so as to minimize likelihood of collision. A reader can identify the proper frequency either by a signal from the tags indicated the frequency of the next hop or, when no bi-directional communication is available, by deducing the carrier signal frequency from the start bits of a received frame from the tag and scanning for the shifted carrier signal frequency within a tolerance of the deduced carrier signal frequency.

Abstract: An electronic drug compliance monitoring system and associated methods utilize a pill having an electronic transmission capability and external means for receiving that transmission to sense the presence of the pill in the patient's body or digestive tract.

Abstract: A floating core network for secure isolation of a circuit from an external supply interface is described. Isolation of a core is accomplished through a dynamic current limiting network providing an isolated core voltage to the core; and an isolated supply for the corresponding core that is continuously recharged by the dynamic current limiting network. The dynamic current limiting network can include two control loops, one control loop providing a fixed gate voltage to a p-type transistor supplying current to the isolated supply and another control loop providing a fixed gate voltage to an n-type transistor sinking current from the isolated supply.

Abstract: A power planning phase module, a placement phase module, and a routing phase module are provided that can replace, supplement, or enhance existing electronic design automation (EDA) software tools. The power planning phase module adds distributed power sources and a network of switching elements to the power frame or ring assigned to regions of a chip (that may be identified during a floor planning stage). The placement phase module optimizes a number and type of cells attached to each power source of the distributed power sources already added or to be added during the power planning phase. The routing phase module optimizes routing length to, for example, mask power consumption.

Abstract: A floating core network for secure isolation of a circuit from an external supply interface is described. Isolation of a core is accomplished through a dynamic current limiting network providing an isolated core voltage to the core; and an isolated supply for the corresponding core that is continuously recharged by the dynamic current limiting network. The dynamic current limiting network can include two control loops, one control loop providing a fixed gate voltage to a p-type transistor supplying current to the isolated supply and another control loop providing a fixed gate voltage to an n-type transistor sinking current from the isolated supply.

Abstract: A floating core network for secure isolation of a circuit from an external supply interface is described. Isolation of a core is accomplished through a dynamic current limiting network providing an isolated core voltage to the core; and an isolated supply for the corresponding core that is continuously recharged by the dynamic current limiting network. The dynamic current limiting network can include two control loops, one control loop providing a fixed gate voltage to a p-type transistor supplying current to the isolated supply and another control loop providing a fixed gate voltage to an n-type transistor sinking current from the isolated supply.

Abstract: Ingestible bio-telemetry communication network and associated systems are described. The communication network can include one or more ingestible bio-telemetry tags; and a reader, wherein each of the one or more ingestible bio-telemetry tags generates an out-link signal comprising, for each bit of data in a frame, a pulse reverse keyed symbol. Multiple ingestible bio-telemetry tags can be managed at the same time by allowing the frequency of the transmit carrier signal to change, or “hop” to different frequencies so as to minimize likelihood of collision. A reader can identify the proper frequency either by a signal from the tags indicated the frequency of the next hop or, when no bi-directional communication is available, by deducing the carrier signal frequency from the start bits of a received frame from the tag and scanning for the shifted carrier signal frequency within a tolerance of the deduced carrier signal frequency.

Abstract: A floating core network for secure isolation of a circuit from an external supply interface is described. Isolation of a core is accomplished through a dynamic current limiting network providing an isolated core voltage to the core; and an isolated supply for the corresponding core that is continuously recharged by the dynamic current limiting network. The dynamic current limiting network can include two control loops, one control loop providing a fixed gate voltage to a p-type transistor supplying current to the isolated supply and another control loop providing a fixed gate voltage to an n-type transistor sinking current from the isolated supply.

Abstract: Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.

Abstract: Disclosed is a novel circuit able to generate any logic combination possible as a function of the input logic signals. The circuit is described as a 2 input logistic map circuit but may be expanded to 3 or more inputs as required. Further disclosed is a universal logic array with variable circuit topology. A metallization layer and/or a via interconnection between cells in the array elements produce a circuit topology that implements a Boolean function and/or chaotic function and/or a logic function. The novel circuit provides a circuit topology for secure applications with no obvious physical correspondence between control signal values and input to output mapping. Further disclosed is a network which has a power signature independent of input signal state and output transition. This provides a very useful circuit to protect data from decryption from power signature analysis in secure applications.

Abstract: Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.

Abstract: Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.

Abstract: Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.