Abstract: Disclosed is a system and method for processing a data access request (DAR). A processing unit, such as a storage controller, receives a DAR, indicating data to return on a channel, such as a channel connecting to a host system, and priority information for the received DAR. The processing unit retrieves the requested data for the received DAR from a memory area, such as a cache or direct access storage device (DASD), and determines whether there is a queue of data entries indicating retrieved data for DARs to transfer on the channel. The queued DARs include priority information. The processing unit processes at least one data entry in the queue, the priority information for the data entry, and the priority information for the received DAR to determine a position in the queue for the received DAR. The processing unit then indicates that the received DAR is at the determined position in the queue and processes the queue to select retrieved data to transfer on the channel to the host system.

Abstract: Disclosed is a system for handling an input/output (I/O) operation. A controller, such as a storage controller, receives an I/O operation against an address for an I/O device, such as a volume in a storage system. The controller determines whether there is at least one active I/O operation executing against the I/O device. After determining that there is at least one active I/O operation, the controller determines whether the received I/O operation conflicts with active I/O operations executing against the I/O device. The controller then executes the received I/O operation against the I/O device concurrently with the active I/O operations after determining that the received I/O operation does not conflict with active I/O operations.

Abstract: Aspects for caching storage data include partitioning a storage cache to include a compressed data partition and an uncompressed data partition, and adjusting a size of the compressed data partition and the uncompressed data partition for chosen performance characteristics. A data caching system aspect in a data processing system having a host system in communication with a storage system includes at least one storage device and at least one partially compressed cache. The at least one partially compressed cache further includes an uncompressed partition and a compressed partition, where the compressed partition stores at least a victim data unit from the uncompressed partition.

Abstract: Disclosed is a system for indicating system capabilities. A first processing unit, such as a control unit, receives a command from a second processing unit, such as a host system, indicating capabilities of the first processing unit. The first processing unit determines common capabilities indicated in the command that are also available in the first processing unit and indicates in a data structure, such as a bitmap data structure, the common capabilities. The first processing unit then signals the second processing unit of the change in system status.

Abstract: Disclosed is a system for handling errors. A system managed by a processor processes an error in the system. The system then generates an interrupt to the processor indicating that an error occurred and executes an error mode before the processor interprets the interrupt. As part of the error mode, the system prevents data from transferring between the system and the processor and processes a read request from the processor to the system by returning data to the processor unrelated to the requested data. The processor would then process the interrupt indicating the error and execute a diagnostic mode to diagnose the error in the system.

Abstract: Disclosed is a system for dynamically assigning alias addresses to base addresses referencing an I/O device, such as a direct access storage device (DASD). In the system, at least one base control block indicates a base address and a plurality of alias control blocks indicate a plurality of alias addresses. Each control block is associated with an address for addressing an I/O device. A processing unit, such as a host computer system, processes at least one alias control block associated with the I/O device and determines a base control block associated with the I/O device with which the alias control blocks are associated. The processing unit then binds at least one alias control block to the determined base control block. The bound base and alias control blocks provide different addresses to address the same I/O device.

Abstract: A converter system that allows a host system using a first interface to use a second storage using a second interface. The invention provides a method to allow an ECKD MVS DASD storage using an ESCON interface to be used by an open system using a SCSI-type interface without changes to the ESCON storage or the open storage interfaces. The method also permits the SCSI-type interfaced open system to be physically located greater than 25 meters from the ESCON storage system. The method involves mapping the SCSI-type interface data and commands into parameters used and understood by the ESCON storage. The invention may also be implemented to provide a digital data storage medium containing the method of the invention and a digital apparatus capable of executing the invention.

Abstract: Disclosed is a system for performing input/output (I/O) operations with a processing unit. A processing unit, such as a host system, determines a base and associated alias addresses to address an I/O device, such as a direct access storage device (DASD). The processing unit associates the determined base and alias addresses to the I/O device. The association of base and alias addresses is maintained constant for subsequent I/O operations until the processing unit detects a reassignment of the association of base and alias addresses. The processing unit then determines an available base or alias address to use with an I/O operation and may concurrently execute multiple I/O operations against the I/O device using the base and alias addresses.

Abstract: Disclosed is a system for reassigning addresses. A first processing unit, such as a storage controller, provides at least two base addresses for addressing devices, such as volumes of a direct access storage device (DASD) and a plurality of alias addresses. An alias address associated with a base address provides an address for addressing the device addressed by the base address. The first processing unit processes a command transmitted from a second processing unit, such as a host system that accesses the DASD through the storage controller, to reassign an alias address from a first base address to a second base address. The first base address addresses a first device and the second base address addresses a second device. The first processing unit then indicates that the alias address to reassign is not associated with the first base address and is associated with the second base address. The second device addressed by the second base addresses is capable of being addressed by the reassigned alias address.

Abstract: Disclosed is a cache management scheme using multiple data structure. A first and second data structures, such as linked lists, indicate data entries in a cache. Each data structure has a most recently used (MRU) entry, a least recently used (LRU) entry, and a time value associated with each data entry indicating a time the data entry was indicated as added to the MRU entry of the data structure. A processing unit receives a new data entry. In response, the processing unit processes the first and second data structures to determine a LRU data entry in each data structure and selects from the determined LRU data entries the LRU data entry that is the least recently used. The processing unit then demotes the selected LRU data entry from the cache and data structure including the selected data entry. The processing unit adds the new data entry to the cache and indicates the new data entry as located at the MRU entry of one of the first and second data structures.

Abstract: Disclosed is a system for communication among a device, a first processor, and a second processor. One of a first data path and second data path is configured. The first data path comprises a bus, such as a local PCI bus, a first remote bridge, and a first local bridge. The bridges may be comprised of PCI to PCI bridges. After configuring the first data path, the device communicates to the first processor by communicating data through the bus to the first remote bridge. The first remote bridge transmits the data to the first local bridge and the first local bridge transmits the data to the first processor. The second data path comprises the bus, a second remote bridge, and a second local bridge. After configuring the second data path, the device communicates to the second processor by communicating data through the bus to the second remote bridge. The second remote bridge transmits the data to the second local bridge and the second local bridge transmits the data to the second processor.

Abstract: In summary, preferred embodiments disclose a system, method, and program for data transfer commands to perform data transfer operations between a first processing unit and second processing unit. The second processing unit controls access to a storage system. The storage system storage space is logically divided into multiple tracks. Each track includes one or more data records. Each data record includes an index area providing index information on the content of the data record and a user data area including user data. An initialization command is communicated from the first processing unit to the second processing unit indicating a range of tracks on which data transfer operations will be performed. For each track in the range of tracks, a set of data transfer operations is executed. This set of data transfer operations includes transmitting a data transfer command from the first processing unit to the second processing unit.

Abstract: A data storage system and method for securely storing data includes (a) a host CPU; (b) a non-volatile storage (NVS) memory for storing data; (c) a processor, the processor being coupled to the host CPU and the NVS memory and monitoring availability of space in the NVS memory and in a non-volatile buffer (NV-Buffer); and (d) the NV-Buffer, the NV-Buffer being coupled to the host CPU, the NVS memory, and the processor, upon receiving a request to write data into the NVS memory, the host CPU storing data to be transferred to the NVS memory into the NV-Buffer, and upon receiving a confirmation message that data of a write operation to the NV-Buffer is committed, the NV-Buffer transferring the data to the NVS memory. The NVS memory includes a fast dump space for storing data transferred from the NV-Buffer when a main power is down and for restoring back data from the NVS memory to the NV-Buffer when the power is up.

Abstract: A data storage system provides generalized record caching through a control unit adapted to support track caching in the upper level store of a two level memory. Dynamic reallocation of space between each type of caching in the upper store follows operating patterns of host computer systems using the data storage system. A storage controller cache has a plurality of segments. A directory data entry data structure is allocated each segment. Such allocated directory entries are used to identify tracks as cached. A plurality of unallocated directory entries are also provided. As a record is cached in a segment outside of a track slot, an unallocated directory entry is used to identify a virtual track in cache corresponding to the track of the record in the lower level store. Records from one track can thus appear in several segments outside track slots.

Abstract: A method for operating a controller for a plurality of direct access storage devices to minimize rotational misses during data transfer operations. Transferred data is staged into a controller cache when a rotational position sensing miss avoidance reconnection is made. Circumstances are detailed for qualifying an operation pending on direct access storage devices for treatment as miss avoidance candidates. Adjustment of controller response depending upon foreknowledge that a channel command word chain includes a write operation is also accomplished utilizing the present method.

Abstract: An improved storage controller and method for storing and recovering data. The storage controller includes a first cluster for directing data from a host computer to a storage device and a second cluster for directing data from a host computer to a storage device. A first cache memory is connected to the first cluster and a second cache memory is connected to the second cluster. A first nonvolatile memory is connected to the second cluster and a second nonvolatile memory is connected to the first cluster. The first and second cache memories and the first and second nonvolatile stores are thus "cross-coupled" to the first and second clusters to provide improved data recovery capability. Data is directed to the first cache and backed up to the first nonvolatile memory in a first operational mode. In the event of failure of the first nonvolatile memory, data is recovered from the first cache memory.

Abstract: A method and system for enhancing the efficiency of communication between one or more host computers and a storage system controller during a data search within either the associated storage systems or within the storage system controller itself. A storage system controller, coupled to one or more host computers via multiple communication channels, is utilized to control access to one or more direct access storage devices. A host computer authorizes the storage system controller to search within a range of data locations within the storage system, sets an initial location from which the data search will begin, and specifies a key field argument to search for. The host computer then permits the storage system controller to independently search the authorized range of data locations within the storage system or within cache memory within the storage system controller.

Abstract: The invention teaches a system and method for temporarily buffering data written to a storage system by a host computer. The storage system includes direct access storage devices and a cache. The cache is used as the buffer for both caching and noncaching data records before destaging to a direct access storage device. Upon receipt of a channel program from a host computer containing data for records to be updated, the storage controller determines if the records are currently cached. If the records are not cached, a write miss has occurred. Upon a write miss the storage controller checks an attribute transmitted in the channel program to determine if the records have a regular format. Records having a known, regular format are buffered in cache until destaged by a background process.

Abstract: A remote copy system incorporates dynamically modifiable ports on the storage controllers such that those ports can operate either as a control unit link-level facility or as a channel link-level facility. When configured as a channel link-level facility, a primary storage controller can appear as a host processor to a secondary storage controller. The primary storage controller can thereafter initiate multiple request connects (RQC) concurrently for servicing a single I/O request. In this manner, a first available path can be selected and system throughput thus improved since RQCs so not need to be sent serially from path to path looking for an available path.

Abstract: A method and system for controlling data flow in a storage subsystem containing multiple cache and/or multiple NVS elements based on the operability of the cache arrays and NVS arrays. In a data processing system having a storage controller connecting a plurality of host processors and a plurality of storage devices, this invention provides a method and architecture for managing multiple storage elements within the controller, without a degradation in subsystem performance and without data integrity problems. A set of configuration registers is utilized by the microcontroller to direct cache and NVS access to the proper storage array. A configuration table is loaded with status information concerning the memory arrays at Initial Microcode Load(IML) and this information is periodically updated during controller operation.