Abstract: Spurious energy suppression for a data communication system is achieved without using a large order noise suppression filter, by means of a post-mixer tracking filter that contains a current-controlled MOSFET-implemented resistance for a transconductance-capacitance filter and an associated transconductance tuning stage. The MOSFET-implemented resistance is controlled by the same control current that establishes the output frequency. As a result, the cut-off frequency of the tracking filter is linearly proportional to the carrier and independent of absolute processing parameters and temperature.

Abstract: Spurious energy suppression for a data communication system is achieved without using a large order noise suppression filter, by means of a post-mixer tracking filter that contains a current-controlled MOSFET-implemented resistance for a transconductance-capacitance filter and an associated transconductance tuning stage. The MOSFET-implemented resistance is controlled by the same control current that establishes the output frequency. As a result, the cut-off frequency of the tracking filter is linearly proportional to the carrier and independent of absolute processing parameters and temperature.

Abstract: A digital-to-analog conversion method and interpolating digital-to-analog converter for a data modulation system which reduces the spurious energy content of the output signal by an order of magnitude to thereby permit use of a less complex reconstruction filter to smooth the analog output. The process is a two step charge redistribution with feedback to interpolate between samples. DC offset is minimized by using double sampling techniques which permit a fully held signal between interpolation samples. A first conversion stage converts the first n bits of an N bit data signal received at an input rate to a first output value, and a second conversion stage converts the remainder of the N bits and combines signals from the two conversion stages to provide a combined output to an interpolation stage which provides an interpolated output at an interpolation output rate. A feedback circuit provides the interpolated output to an input of the second conversion stage.

Abstract: Spurious energy suppression for a data communication system is achieved without using a large order noise suppression filter, by means of a pre-mixer tracking filter incorporated into an emitter-coupled logic configured buffer of a carrier frequency generator, using a MOSFET-implemented current-controlled resistance component of a resistor-capacitor network and an associated current control stage. The MOSFET-implemented resistance components of the filter are controlled by the same control current that establishes the carrier generator's output frequency. As a result, the cut-off frequency of the tracking filter is linearly proportional to the carrier and effectively independent of process parameters.

Abstract: The noise performance of a non-linear circuit design is measured prior to circuit fabrication by a circuit modelling and analysis mechanism, which simulates each noise source as a reduced complexity continuous Gaussian noise waveform. A respective noise source (e.g. thermal or shot) is modelled as a time domain sequence of continuously connected third order polynomial signal waveforms, forming a cubic spline that interconnects successively occurring Gaussian signal amplitude values. For each type of noise source, its associated Gaussian function is determined by the product of the constant multipliers associated with that type of source. The number of points processed for each noise source depends upon the time width of a noise analysis window.

Abstract: A circuit and method for adjusting a cutoff frequency of an active filter, such as a gm-C filter, which has a common mode feedback circuit for providing a bias signal may include plural common base stages having first inputs connected in parallel to a stage of the active filter and second inputs connected in parallel to an output from the common mode feedback circuit, and a capacitor connected to an output from each of the common base stages. The common base stages and their connected capacitors are selectively isolated from the filter output to adjust the cutoff frequency of the filter. The deselected common base stages are also isolated from the common mode feedback circuit and bias generator inputs.

Abstract: A loop filter for a phase locked loop (PLL) circuit may include two operational amplifiers and switched-capacitors connecting the inverted input and output of the operational amplifiers, the switched-capacitors replacing resistors found in conventional loop filters for PLL circuits. The loop filter may be in a monolithic integrated circuit, and the PLL circuit may operate with a response time heretofore available only with individual (non-IC) components. Phase error due to amplifier offset may be reduced with offset nulling techniques.

Abstract: A method and circuit for tuning an equivalent resistor in a filter so that the filter is insensitive to temperature changes in which an amplifier output is connected to a common gate of plural MOSFETs for providing equivalent resistances, and in which one input to the amplifier is connected to a reference resistor and the other input to the amplifier is connected to an equivalent resistor that includes one of the plural MOSFETs. An input current to the reference resistor and to the equivalent resistor's MOSFET is inversely proportional to the MOSFET's conduction parameter, k (i.e., .mu.C.sub.ox /2), so that both the inputs to the amplifier vary to change the amplifier output voltage to the common gate. The amplifier output changes render the filter insensitive to temperature changes.

Abstract: Impulse noise suppression upstream of digital processing circuitry contains a sample and hold mechanism which samples the input signal and stores a plurality of sequential sample values respectively representative of the amplitude of the input signal at successive sample times. The contents of the sample and hold mechanism are compared with an input signal sample to determine whether or not the there are abnormal amplitude variations which potentially constitute impulse noise. In one embodiment the comparison is referenced to the average magnitude of the input signal. In another embodiment the input signal is coupled to a cascaded arrangement of sample and hold circuits which sample and store a plurality of sequential sample values. The time differentials between successive sampling times are such there is little likelihood of occurrences of impulse noise spikes during any two successive sample intervals.

Abstract: A transimpedance processor includes a feedback circuit for generating a voltage as a function of the input background level and precharging the capacitor of the input integrator to a negative of the generated voltage in a precharge cycle.

Abstract: A CMOS limiter with input hysteresis, responsive to an input signal of varying amplitude, produces an output signal which changes between at least first and second levels, the transitions occurring when the absolute value of the amplitude of the input signal exceeds predetermined reference level. The limiter is fabricated on a single integrated circuit using CMOS switched capacitor techniques. An SC switching array selects between sampled input signal and an inverted sampled input signal depending upon the value of the output signal produced by the limiter. A comparing network (comprising an active CMOS comparator responsive to a difference signal produced at a summing node) changes the level of the output signal of the limiter when the selected signal exceeds a predetermined reference value. The summing node includes a signal level storing device (i.e. a precision capacitor) for storing the reference level during the period in which the input signal is sampled.