Patents by Inventor Brent R. Blaes

Brent R. Blaes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7772550
    Abstract: The present invention discloses an mixed signal RF drive electronics board that offers small, low power, reliable, and customizable method for driving and generating mass spectra from a mass spectrometer, and for control of other functions such as electron ionizer, ion focusing, single-ion detection, multi-channel data accumulation and, if desired, front-end interfaces such as pumps, valves, heaters, and columns.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: August 10, 2010
    Assignee: California Institute of Technology
    Inventors: Rembrandt Thomas Schaefer, Mohammad Mojarradi, Ara Chutjian, Murray R. Darrach, John MacAskill, Tuan Tran, Gary R. Burke, Stojan M. Madzunkov, Brent R. Blaes, John L. Thomas, Ryan A. Stern, David Q. Zhu
  • Patent number: 6462983
    Abstract: A non-volatile magnetic random access memory (RAM) system having a semiconductor control circuit and a magnetic array element. The integrated magnetic RAM system uses CMOS control circuit to read and write data magnetoresistivity. The system provides a fast access, non-volatile, radiation hard, high density RAM for high speed computing.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: October 8, 2002
    Assignee: California Institute of Technology
    Inventors: Romney R. Katti, Brent R. Blaes
  • Publication number: 20020021580
    Abstract: The present disclosure describes a non-volatile magnetic random access memory (RAM) system having a semiconductor control circuit and a magnetic array element. The integrated magnetic RAM system uses CMOS control circuit to read and write data magnetoresistively. The system provides a fast access, non-volatile, radiation hard, high density RAM for high speed computing.
    Type: Application
    Filed: April 3, 2001
    Publication date: February 21, 2002
    Applicant: California Institute of Technology
    Inventors: Romney R. Katti, Brent R. Blaes
  • Patent number: 6219273
    Abstract: The present disclosure describes a non-volatile magnetic random access memory (RAM) system having a semiconductor control circuit and a magnetic array element. The integrated magnetic RAM system uses CMOS control circuit to read and write data magnetoresistively. The system provides a fast access, non-volatile, radiation hard, high density RAM for high speed computing.
    Type: Grant
    Filed: March 2, 1999
    Date of Patent: April 17, 2001
    Assignee: California Institute of Technology
    Inventors: Romney R. Katti, Brent R. Blaes
  • Patent number: 5753920
    Abstract: An integrated charge monitor for measuring a level of cumulative radiation exposure includes semiconductor devices having characteristics that change with a cumulative level of radiation to which the devices are exposed, different amounts of radiation shielding associated with each of the devices, and circuitry operable to separately address each of the devices to measure a change in the characteristic of the selected device due to radiation exposure. The monitor may be implemented on a single integrated circuit chip. The monitor may also be employed in performing a spectrometric analysis of radiation based on the affect of the radiation on characteristics of multiple, differently-shielded semiconductor devices.
    Type: Grant
    Filed: July 26, 1995
    Date of Patent: May 19, 1998
    Assignee: California Institute of Technology
    Inventors: Martin G. Buehler, Brent R. Blaes, George A. Soli
  • Patent number: 5396169
    Abstract: A method for predicting the SEU susceptibility of a standard-cell D-latch using an alpha-particle sensitive SRAM, SPICE critical charge simulation results, and alpha-particle interaction physics. A technique utilizing test structures to quickly and inexpensively characterize the SEU sensitivity of standard cell latches intended for use in a space environment. This bench-level approach utilizes alpha particles to induce upsets in a low LET sensitive 4-k bit test SRAM. This SRAM consists of cells that employ an offset voltage to adjust their upset sensitivity and an enlarged sensitive drain junction to enhance the cell's upset rate.
    Type: Grant
    Filed: October 5, 1992
    Date of Patent: March 7, 1995
    Assignee: Lynx Golf Inc.
    Inventors: Martin G. Buehler, Brent R. Blaes, Robert H. Nixon, George A. Soli
  • Patent number: 5332903
    Abstract: A p-MOSFET total dose dosimeter where the gate voltage is proportional to the incident radiation dose. It is configured in an n-WELL of a p-BODY substrate. It is operated in the saturation region which is ensured by connecting the gate to the drain. The n-well is connected to zero bias. Current flow from source to drain, rather than from peripheral leakage, is ensured by configuring the device as an edgeless MOSFET where the source completely surrounds the drain. The drain junction is the only junction not connected to zero bias. The MOSFET is connected as part of the feedback loop of an operational amplifier. The operational amplifier holds the drain current fixed at a level which minimizes temperature dependence and also fixes the drain voltage. The sensitivity to radiation is made maximum by operating the MOSFET in the OFF state during radiation soak.
    Type: Grant
    Filed: November 30, 1992
    Date of Patent: July 26, 1994
    Assignee: California Institute of Technology
    Inventors: Martin G. Buehler, Brent R. Blaes
  • Patent number: 5331164
    Abstract: A particle sensor array which in a preferred embodiment comprises a static random access memory having a plurality of ion-sensitive memory cells, each such cell comprising at least one pull-down field effect transistor having a sensitive drain surface area (such as by bloating) and at least one pull-up field effect transistor having a source connected to an offset voltage. The sensitive drain surface area and the offset voltage are selected for memory cell upset by incident ions such as alpha-particles. The static random access memory of the present invention provides a means for selectively biasing the memory cells into the same state in which each of the sensitive drain surface areas is reverse biased and then selectively reducing the reversed bias on these sensitive drain surface areas for increasing the upset sensitivity of the cells to ions. The resulting selectively sensitive memory cells can be used in a number of applications.
    Type: Grant
    Filed: March 19, 1991
    Date of Patent: July 19, 1994
    Assignee: California Institute of Technology
    Inventors: Martin G. Buehler, Brent R. Blaes, Udo Lieneweg
  • Patent number: 4688947
    Abstract: Propagation delay of a signal through a channel is measured by cyclically generating a first step-wave signal for transmission through the channel to a two-input logic element and a second step-wave signal with a controlled delay to the second input terminal of the logic element. The logic element determines which signal is present first at its input terminals and stores a binary signal indicative of that determination for control of the delay of the second signal which is advanced or retarded for the next cycle until both the propagation delayed first step-wave signal and the control delayed step-wave signal are coincident. The propagation delay of the channel is then determined by measuring the time between the first and second step-wave signals out of the controlled step-wave signal generator.
    Type: Grant
    Filed: February 18, 1986
    Date of Patent: August 25, 1987
    Assignee: California Institute of Technology
    Inventors: Brent R. Blaes, Martin G. Buehler