Patents by Inventor Brent R. Boswell
Brent R. Boswell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10296338Abstract: In one embodiment, a processor includes: an accelerator associated with a first address space; a core associated with a second address space and including an alternate address space configuration register to store configuration information to enable the core to execute instructions from the first address space; and a control logic to configure the core based in part on information in the alternate address space configuration register. Other embodiments are described and claimed.Type: GrantFiled: December 9, 2016Date of Patent: May 21, 2019Assignee: Intel CorporationInventors: Brent R. Boswell, Banu Meenakshi Nagasundaram, Michael D. Abbott, Srikanth Dakshinamoorthy, Jason M. Howard, Joshua B. Fryman
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Patent number: 10282341Abstract: Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.Type: GrantFiled: August 8, 2017Date of Patent: May 7, 2019Assignee: Intel CorporationInventors: Bryan L. Spry, Marcus W. Song, Deepak M. Rangaraj, Avinash N. Ananthakrishnan, Robert J. Hayes, Aimee D. Wood, Adam E. Letendre, Brent R. Boswell
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Publication number: 20180210857Abstract: Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.Type: ApplicationFiled: August 8, 2017Publication date: July 26, 2018Inventors: Bryan L. Spry, Marcus W. Song, Deepak M. Rangaraj, Avinash N. Ananthakrishnan, Robert J. Hayes, Aimee D. Wood, Brent R. Boswell
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Publication number: 20180165203Abstract: In one embodiment, a processor includes: an accelerator associated with a first address space; a core associated with a second address space and including an alternate address space configuration register to store configuration information to enable the core to execute instructions from the first address space; and a control logic to configure the core based in part on information in the alternate address space configuration register. Other embodiments are described and claimed.Type: ApplicationFiled: December 9, 2016Publication date: June 14, 2018Inventors: Brent R. Boswell, Banu Meenakshi Nagasundaram, Michael D. Abbott, Srikanth Dakshinamoorthy, Jason M. Howard, Joshua B. Fryman
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Patent number: 9734116Abstract: Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.Type: GrantFiled: March 13, 2015Date of Patent: August 15, 2017Assignee: Intel CorporationInventors: Bryan L. Spry, Marcus W. Song, Deepak M. Rangaraj, Avinash N. Ananthakrishnan, Robert J. Hayes, Aimee D. Wood, Adam E. Letendre, Brent R. Boswell
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Publication number: 20150269108Abstract: Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.Type: ApplicationFiled: March 13, 2015Publication date: September 24, 2015Inventors: Bryan L. Spry, Marcus W. Song, Deepak M. Rangaraj, Avinash N. Ananthakrishnan, Robert J. Hayes, Aimee D. Wood, Adam E. Letendre, Brent R. Boswell
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Patent number: 8918446Abstract: Methods and apparatus relating to reducing power consumption in multi-precision floating point multipliers are described. In an embodiment, certain portions of a multiplier are disabled in response to two or more multiplication operations with the same data size and data type occurring back-to-back. Other embodiments are also claimed and described.Type: GrantFiled: December 14, 2010Date of Patent: December 23, 2014Assignee: Intel CorporationInventors: Brent R. Boswell, Thierry Pons, Tom Aviram
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Patent number: 8787565Abstract: An Advanced Encryption Standard (AES) key generation assist instruction is provided. The AES key generation assist instruction assists in generating round keys used to perform AES encryption and decryption operations. The AES key generation instruction operates independent of the size of the cipher key and performs key generation operations in parallel on four 32-bit words thereby increasing the speed at which the round keys are generated. This instruction is easy to use in software. Hardware implementation of this instruction removes potential threats of software (cache access based) side channel attacks on this part of the AES algorithm.Type: GrantFiled: August 20, 2007Date of Patent: July 22, 2014Assignee: Intel CorporationInventors: Shay Gueron, Martin G. Dixon, Srinivas Chennupaty, Mayank Bomb, Brent R. Boswell
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Publication number: 20120151191Abstract: Methods and apparatus relating to reducing power consumption in multi-precision floating point multipliers are described. In an embodiment, certain portions of a multiplier are disabled in response to two or more multiplication operations with the same data size and data type occurring back-to-back. Other embodiments are also claimed and described.Type: ApplicationFiled: December 14, 2010Publication date: June 14, 2012Inventors: Brent R. Boswell, Thierry Pons, Tom Aviram
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Patent number: 7366881Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.Type: GrantFiled: April 11, 2005Date of Patent: April 29, 2008Assignee: Intel CorporationInventors: Patrice Roussel, Glenn J. Hinton, Shreekant S. Thakkar, Brent R. Boswell, Karol F. Menezes
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Patent number: 6925553Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a macro instruction specifying an operation, and specifying a first and a second data operand in first and second registers, respectively, is received. The macro instruction is then split into a first micro instruction and a second micro instruction, the first micro instruction specifying the operation on a first corresponding segment including a first portion of the first data operand and a first portion of the second data operand, and the second micro instruction specifying the operation on a second corresponding segment including a second portion of the first data operand and a second portion of the second data operand. The first and second micro instructions are then executed.Type: GrantFiled: October 20, 2003Date of Patent: August 2, 2005Assignee: Intel CorporationInventors: Patrice Roussel, Glenn J. Hinton, Shreekant S. Thakkar, Brent R. Boswell, Karol F. Menezes
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Publication number: 20040083353Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a macro instruction specifying an operation, and specifying a first and a second data operand in first and second registers, respectively, is received. The macro instruction is then split into a first micro instruction and a second micro instruction, the first micro instruction specifying the operation on a first corresponding segment including a first portion of the first data operand and a first portion of the second data operand, and the second micro instruction specifying the operation on a second corresponding segment including a second portion of the first data operand and a second portion of the second data operand. The first and second micro instructions are then executed.Type: ApplicationFiled: October 20, 2003Publication date: April 29, 2004Inventors: Patrice Roussel, Glenn J. Hinton, Shreekant S. Thakkar, Brent R. Boswell, Karol F. Menezes
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Patent number: 6694426Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.Type: GrantFiled: June 6, 2002Date of Patent: February 17, 2004Assignee: Intel CorporationInventors: Patrice Roussel, Glenn J. Hinton, Shreekant S. Thakkar, Brent R. Boswell, Karol F. Menezes
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Patent number: 6687810Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.Type: GrantFiled: June 6, 2002Date of Patent: February 3, 2004Assignee: Intel CorporationInventors: Patrice Roussel, Glenn J. Hinton, Shreekant S. Thakkar, Brent R. Boswell, Karol F. Menezes
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Publication number: 20020184474Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.Type: ApplicationFiled: June 6, 2002Publication date: December 5, 2002Inventors: Patrice Roussel, Glenn J. Hinton, Shreekant S. Thakkar, Brent R. Boswell, Karol F. Menezes
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Publication number: 20020178348Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.Type: ApplicationFiled: June 6, 2002Publication date: November 28, 2002Inventors: Patrice Roussel, Glenn J. Hinton, Shreekant S. Thakkar, Brent R. Boswell, Karol F. Menezes
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Patent number: 6425073Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.Type: GrantFiled: March 13, 2001Date of Patent: July 23, 2002Assignee: Intel CorporationInventors: Patrice Roussel, Glenn J. Hinton, Shreekant S. Thakkar, Brent R. Boswell, Karol F. Menezes
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Patent number: 6230257Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.Type: GrantFiled: March 31, 1998Date of Patent: May 8, 2001Assignee: Intel CorporationInventors: Patrice Roussel, Glenn J. Hinton, Shreekant S. Thakkar, Brent R. Boswell, Karol F. Menezes