Abstract: Embodiments herein relate to a sampling phase-locked loop (PLL) with a compensation circuit for reducing ripples due to the use of a fractional N divider. The compensation circuit includes a ripple amplifier and a ripple divider. The ripple amplifier receives an output voltage, Vmain, of a main sampling circuit of the PLL and amplifies its alternating current (AC) components. The amplified output voltage is provided to a ripple integrator which samples the minimum and maximum values to provide inputs to an operational amplifier (op amp). An output of the op amp is fed back to a digital-to-analog converter (DAC), which provides a corresponding compensation voltage, Vcomp. Vcomp is added to Vmain to provide a final output control voltage, Vctrl, to control a voltage-controlled oscillator (VCO) of the PLL.

Abstract: A radiofrequency frontend device includes a memory array, which includes a plurality of input lines; a plurality of output lines; and a plurality of impedance devices, each impedance device connecting an input line of the plurality of input lines to an output line of the plurality of output lines, wherein each impedance represents a filter coefficient; wherein the radiofrequency frontend device is configured to provide at each input line of the plurality of input lines a sampled voltage of an analog electric signal, each sampled voltage corresponding to a voltage of the analog electric signal during a respective time period of a plurality of time periods; and when the memory array receives the sampled voltages, the memory array is configured to modify each of the sampled voltages by a respective impedance device of the plurality of impedance devices and sum the modified sampled voltages.

Abstract: A converter can include a number of time-to-voltage converters (TVCs) each receiving an input time-domain signal. The input time-domain signal can represent a different sample than input time-domain signals of the other TVCs. The converter can also include a capacitive element coupled to outputs of the TVCs to receive a combined output signal of the TVCs. The capacitive element can provide an input capacitance of an analog-to-digital converter (ADC). Other methods and apparatuses are described.

Abstract: An apparatus, system, and method for multi-frequency oscillator control are provided. A circuit can include a resonator circuit including an input and an output, the resonator circuit configured to resonate at a fundamental frequency and a different, non-fundamental frequency, a startup circuit electrically coupled to the input, the startup circuit configured to generate a signal at about the non-fundamental frequency and detect when the resonator circuit is resonating at the non-fundamental frequency, and an oscillator driver circuit electrically coupled to the output, the oscillator driver circuit configured to amplify and buffer the output of resonator circuit and drive a load.

Abstract: In various aspects, a device-to-device communication system is provided including a first device and a second device. Each of the first device and the second device includes an antenna, a radio frequency frond-end circuit, and a baseband circuit. Each of the first device and the second device are at least one of a chiplet or a package. The device-to-device communication system further includes a cover structure housing the first device and the second device. Each of the first device and the second device are at least one of a chiplet or a package. The device-to-device communication system further includes a radio frequency signal interface wirelessly communicatively coupling the first device and the second device. The radio frequency signal interface includes the first antenna and the second antenna.

Abstract: An apparatus, system, and method for are provided. A device includes a time-to-digital converter (TDC) situated to convert a time-domain signal to a digital value, a delay circuit situated in parallel with the TDC and to delay the time-domain signal by a specified amount of time resulting in a delayed time-domain signal, a time-to-voltage converter (TVC) situated to produce a voltage-domain signal based on the delayed time-domain signal, and a successive approximation (SAR) circuit situated to receive the digital value and the voltage-domain signal and produce a digital-domain version of the input signal.

Abstract: An apparatus can include a digital-to-analog converter (DAC) and calibration circuitry including an oscillator. The calibration circuitry can be coupled to an output of the DAC, the calibration circuitry to sample and count DAC output pulses for at least two consecutive pulses using at least two separate counter circuits. The calibration circuitry can determine error between at least two consecutive pulses and provide a correction value based on the error. The apparatus can further include correction circuitry to provide a calibration signal to the DAC based on the correction value.

Abstract: A differential voltage-to-time converter (VTC) architecture and method of providing VTC signals are disclosed. The VTC includes a ramp generator that generates a ramp voltage, capacitors having a bottom plate coupled with the ramp generator to receive the ramp voltage, and inverters having inputs coupled to top plates of the capacitors to provide signals based on a sampled signal. A threshold voltage or supply voltage of the inverters tracks a minimum input signal voltage.

Abstract: A digital-to-time converter (DTC)-based open loop frequency synthesis and calibration circuit may be used to provide a precise clock signal. The DTC calibration circuit may include a DTC to generate a DTC clock signal based on a received input clock frequency and a received initial digital input code, a phase-lock loop (PLL) to generate a PLL clock signal based on a received PLL input, a binary phase-detector (PD) to generate a PD output based on a comparison between the DTC clock signal and the PLL clock signal, a plurality of calibration bins to generate a signed accumulated PD portion based on the PD output, and an adder to generate a calibrated DTC input code based on a combination of the signed accumulated PD portion and a subsequent digital input code, where the DTC generates a calibrated clock signal based on the calibrated DTC input code.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a MEMS die located within a substrate, and below a processor die. In selected examples, the MEMS die includes a resonator. Example methods of forming MEMS resonator devices are also shown.

Abstract: A transceiver may include a transmitter device, a receiver device, a secondary receiver device, and switching elements. The transmitter device may provide a transmit control signal on first and second channels. The receiver device may receive a receive control signal on the first and second channels. The secondary receiver device may monitor occupation of the first and second channels without decoding at least a portion of control signals concurrent with the receiver device receiving the receive control signal. The switching elements may control when the transmitter device provides the transmit control signal to one of and is electrically isolated from first and second antennas, the receiver device receives the receive control signal from one of and is electrically isolated from the first and second antennas, and the secondary receiver device monitors occupation of one of the first and second channels and is electrically isolated from the first and second antennas.

Abstract: Various aspects provide a transceiver and a communication device including the transceiver. In an example, the transceiver includes an amplifier circuit including an amplifier stage with an adjustable degeneration component, the amplifier stage configured to amplify a received input signal with an adjustable gain, an adjustable feedback component coupled to the amplifier stage; and a controller coupled to the amplifier stage and to the adjustable feedback component and configured to adjust the adjustable feedback component based on an adjustment of the adjustable degeneration component.

Abstract: Embodiments of apparatuses, articles, methods, and systems for calibrating receive chain to reduce second order intermodulation distortion are disclosed herein. In some embodiments, a reference sensing chain is used to generate reference second-order intermodulation distortion signals that may be used to adjust a calibration code. In some embodiments, a calibration code may be adjusted using one or more feedback loops of a baseband amplifier. The embodiments may be employed, e.g., to manage power in wireless networks. Other embodiments and usages may be described and claimed.

Abstract: Embodiments of apparatuses, articles, methods, and systems for calibrating receive chain to reduce second order intermodulation distortion are disclosed herein. The embodiments may be employed, e.g., to manage power in wireless networks. Other embodiments and usages may be described and claimed.

Abstract: An apparatus and method is disclosed for improving the gain precision and bandwidth of fixed-gain amplifiers, while providing high bandwidth and performance necessary in many applications. Fixed-gain amplifiers, having relatively precise gain, are connected together in a specific architecture to further increase the gain precision and bandwidth over any of the amplifiers operating independently. Due to the configuration of the amplifiers, the absolute gain error of individual amplifiers is substantially canceled such the gain error of the total circuit is greatly reduced. The disclose architecture is useful in many high speed, high bandwidth applications where very precise gain is needed, while avoiding the reduction in bandwidth caused by amplifiers using feedback to achieve gain stability.

Abstract: An apparatus and method is disclosed for improving the gain precision and bandwidth of fixed-gain amplifiers, while providing high bandwidth and performance necessary in many applications. Fixed-gain amplifiers, having relatively precise gain, are connected together in a specific architecture to further increase the gain precision and bandwidth over any of the amplifiers operating independently. Due to the configuration of the amplifiers, the absolute gain error of individual amplifiers is substantially canceled such the gain error of the total circuit is greatly reduced. The disclose architecture is useful in many high speed, high bandwidth applications where very precise gain is needed, while avoiding the reduction in bandwidth caused by amplifiers using feedback to achieve gain stability.