Abstract: A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance.

Abstract: A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance.

Abstract: A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance.

Abstract: A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance.

Abstract: A junction isolated Complementary Metal Oxide Semiconductor (CMOS) transistor device includes a substrate of a first conductivity type and first and second buried layers formed within the substrate and having a second conductivity type opposite from the first conductivity type. First and second well regions of respective first and second conductivity are formed above respective first and second buried layers. An NMOS transistor and PMOS transistor are formed in the respective first and second well regions. The buried layer of the NMOS transistor is at −V (typically ground) and the buried layer of the PMOS transistor is biased at a positive supply voltage and spaced sufficiently from the NMOS transistor to improve single event effects occurrence.

Abstract: An analog comparator architecture has improved immunity to single event effects and variations in input offset voltage. A conventional single analog comparator-based circuit is replaced with plural comparators, driving a “majority vote” logic block. The effective input offset voltage of the multi-comparator design is the middle one of the individual comparators' input offset voltages. A single event upset on any comparator may momentarily perturb its output into the incorrect state; however, the output of the majority voting logic block will remain in the correct state, as only one comparator is upset. In addition, where a heavy ion strike on any comparator's bias current source causes a momentary loss of bias current, this upsets only one comparator, so that the output of the voting logic block is unaffected.

Abstract: The circuit and method translate a logic level input signal to signals at high voltage levels to drive a power device, such as a power MOSFET, while minimizing the power consumption. The circuit for driving the power device includes a low side gate driver, and a high side gate driver adjacent thereto. The high side gate drive includes a high side gate driver logic input, a high side gate driver output, a latch connected between the high side gate driver logic input and the high side gate driver output, and a control circuit receiving an output of the latch and controlling signals from the high side gate driver logic input to the latch based upon the output of the latch.

Abstract: An analog comparator architecture has improved immunity to single event effects and variations in input offset voltage. A conventional single analog comparator-based circuit is replaced with plural comparators, driving a “majority vote” logic block. The effective input offset voltage of the multi-comparator design is the middle one of the individual comparators' input offset voltages. A single event upset on any comparator may momentarily perturb its output into the incorrect state; however, the output of the majority voting logic block will remain in the correct state, as only one comparator is upset. In addition, where a heavy ion strike on any comparator's bias current source causes a momentary loss of bias current, this upsets only one comparator, so that the output of the voting logic block is unaffected.

Abstract: A junction isolated Complementary Metal Oxide Semiconductor (CMOS) transistor device includes a substrate of a first conductivity type and first and second buried layers formed within the substrate and having a second conductivity type opposite from the first conductivity type. First and second well regions of respective first and second conductivity are formed above respective first and second buried layers. An NMOS transistor and PMOS transistor are formed in the respective first and second well regions. The buried layer of the NMOS transistor is at −V (typically ground) and the buried layer of the PMOS transistor is biased at a positive supply voltage and spaced sufficiently from the NMOS transistor to improve single event effects occurrence.

Abstract: The circuit and method translate a logic level input signal to signals at high voltage levels to drive a power device, such as a power MOSFET, while minimizing the power consumption. The circuit for driving the power device includes a low side gate driver, and a high side gate driver adjacent thereto. The high side gate drive includes a high side gate driver logic input, a high side gate driver output, a latch connected between the high side gate driver logic input and the high side gate driver output, and a control circuit receiving an output of the latch and controlling signals from the high side gate driver logic input to the latch based upon the output of the latch.

Abstract: A current mirror having an amplification factor K providing a photocurrent compensation current to a node having a mismatch of junction photocurrent. The load device on the input leg of the current mirror has an area 1/K times the device width of the larger device junction area at the node and a device width ratio with drive device of the input leg of a current mirror equal to the ratio of mismatch J at the node.

Abstract: An STL or ISL logic circuit comprising a plurality of single-input, multiple-output logic gates is provided. Each of these gates has a current source and a transistor including a base, emitter and multiple Schottky diode-to-collector contacts. The bases of the logic gate transistors are tied together to minimize metal interconnect stripes when a fanout greater than that of one gate is needed. Current hogging is reduced by an ohmic collector contact with connects the collector of each transistor together.

Abstract: A complementary pair of vertically aligned, inversely operated transistors formed from a P type substrate, a first N type epitaxial layer, a second N type epitaxial layer and a buried, updiffused P type region between the two epitaxial layers. The impurity concentration of the buried region decreases from its junction with the first epitaxial layer to its junction with the second epitaxial layer whose impurity concentration is less than that of the first epitaxial layer. High impurity concentration N type guard ring and P type base ring are diffused simultaneously with the out diffusion of the buried P type region into the second epitaxial layer. The substrate, first epitaxial layer and buried region constitute the emitter, base, and collector of the inverse vertical PNP transistor and the first epitaxial layer, buried region and second epitaxial layer constitute the emitter, base, and collector of the inverse vertical NPN transistor.