Patents by Inventor Brent S. Stone
Brent S. Stone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10056182Abstract: Embodiments of the present disclosure are directed towards an inductor structure having one or more strips of conductive material disposed around a core. The strips may have contacts at a first end and a second end of the strips, and may be disposed around the core with a gap between the contacts. The inductor structure may be mounted on a surface of a substrate, and one or more traces may be formed in the surface of the substrate to electrically couple two or more of the strips of conductive material to one another to form inductive coils. Other embodiments may be described and/or claimed.Type: GrantFiled: February 6, 2015Date of Patent: August 21, 2018Assignee: Intel CorporationInventors: Gregorio R. Murtagian, Robert L. Sankman, Brent S. Stone, Kaladhar Radhakrishnan, Joshua D. Heppner
-
Patent number: 9674954Abstract: This disclosure relates generally to a chip package assembly arranged to be electrically coupled to a circuit board including a plurality of circuit board contacts. The chip package assembly may include a chip package including a first side and a second side, the second side including a first plurality of contacts arranged to be electrically coupled to the plurality of circuit board contacts and a second plurality of contacts arranged to be electrically coupled to a remote device via a connector assembly.Type: GrantFiled: March 14, 2013Date of Patent: June 6, 2017Assignee: Intel CorporationInventors: Rajasekaran Swaminathan, Donald T. Tran, Brent S. Stone, Ram Viswanath
-
Publication number: 20150155092Abstract: Embodiments of the present disclosure are directed towards an inductor structure having one or more strips of conductive material disposed around a core. The strips may have contacts at a first end and a second end of the strips, and may be disposed around the core with a gap between the contacts. The inductor structure may be mounted on a surface of a substrate, and one or more traces may be formed in the surface of the substrate to electrically couple two or more of the strips of conductive material to one another to form inductive coils. Other embodiments may be described and/or claimed.Type: ApplicationFiled: February 6, 2015Publication date: June 4, 2015Inventors: Gregorio R. Murtagian, Robert L. Sankman, Brent S. Stone, Kaladhar Radhakrishnan, Joshua D. Heppner
-
Publication number: 20140268577Abstract: This disclosure relates generally to a chip package assembly arranged to be electrically coupled to a circuit board including a plurality of circuit board contacts. The chip package assembly may include a chip package including a first side and a second side, the second side including a first plurality of contacts arranged to be electrically coupled to the plurality of circuit board contacts and a second plurality of contacts arranged to be electrically coupled to a remote device via a connector assembly.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Inventors: Rajasekaran Raja Swaminathan, Donald T. Tran, Brent S. Stone, Ram Viswanath
-
Publication number: 20140167900Abstract: Embodiments of the present disclosure are directed towards an inductor structure having one or more strips of conductive material disposed around a core. The strips may have contacts at a first end and a second end of the strips, and may be disposed around the core with a gap between the contacts. The inductor structure may be mounted on a surface of a substrate, and one or more traces may be formed in the surface of the substrate to electrically couple two or more of the strips of conductive material to one another to form inductive coils. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 14, 2012Publication date: June 19, 2014Inventors: Gregorio R. Murtagian, Robert L. Sankman, Brent S. Stone, Kaladhar Radhakrishnan, Joshua D. Heppner
-
Patent number: 7687905Abstract: An integrated circuit package includes a first capacitor supported by a surface of a substrate, and a second capacitor supported by the surface of the substrate. The first capacitor is within a die shadow region, and the second capacitor lies outside of the die shadow region.Type: GrantFiled: February 28, 2008Date of Patent: March 30, 2010Assignee: Intel CorporationInventors: Brent S. Stone, Dustin P. Wood, Kaladhar Radhakrishnan
-
Publication number: 20080142962Abstract: An integrated circuit package includes a first capacitor supported by a surface of a substrate, and a second capacitor supported by the surface of the substrate. The first capacitor is within a die shadow region, and the second capacitor lies outside of the die shadow region.Type: ApplicationFiled: February 28, 2008Publication date: June 19, 2008Inventors: Brent S. Stone, Dustin P. Wood, Kaladhar Radhakrishnan
-
Patent number: 7339263Abstract: An integrated circuit package includes a first capacitor supported by a surface of a substrate, and a second capacitor supported by the surface of the substrate. The first capacitor is within a die shadow region, and the second capacitor lies outside of the die shadow region.Type: GrantFiled: June 28, 2004Date of Patent: March 4, 2008Assignee: Intel CorporationInventors: Brent S. Stone, Dustin P. Wood, Kaladhar Radhakrishnan
-
Patent number: 7220132Abstract: A electrical interface for an electronic package, using lands on the package which are non-planar with metal layers within the package. This non-planar or tilted land grid array (TLGA) package is assembled with a complementary TLGA socket to make electronic connection to the package.Type: GrantFiled: June 28, 2004Date of Patent: May 22, 2007Assignee: Intel CorporationInventors: Brent S. Stone, Michael J. Walk
-
Patent number: 7114959Abstract: A grounded conductive plate in a land grid array package assembly includes a plurality of openings. The openings allow contacts from the socket to pass through to contact a package. The diameter of each opening is customizable to produce desired impedance between the contacts and the conductive plate. Impedance discontinuity seen by signals passing through the socket may be reduced.Type: GrantFiled: August 25, 2004Date of Patent: October 3, 2006Assignee: Intel CorporationInventors: Brent S. Stone, Joel A. Auernheimer
-
Patent number: 7034390Abstract: A fabrication method and semiconductor package provide enhanced performance. The semiconductor package includes a semiconductor die having an integrated circuit (IC), and a substrate having a die side coupled to the IC. A plurality of multi-signal bus bars is coupled to a socket side of the substrate such that the bus bars enable I/O signals to be transported between the substrate and a socket.Type: GrantFiled: September 26, 2003Date of Patent: April 25, 2006Assignee: Intel CorporationInventors: Tim M. Gates, Brent S. Stone
-
Patent number: 7014488Abstract: A socket cover with a recessed center, method for using such a socket cover and system using such a socket cover are described herein.Type: GrantFiled: July 29, 2004Date of Patent: March 21, 2006Assignee: Intel CorporationInventor: Brent S. Stone
-
Patent number: 6724077Abstract: A fabrication method and semiconductor package provide enhanced performance. The semiconductor package includes a semiconductor die having an integrated circuit (IC), and a substrate having a die side coupled to the IC. A plurality of multi-signal bus bars is coupled to a socket side of the substrate such that the bus bars enable I/O signals to be transported between the substrate and a socket.Type: GrantFiled: November 9, 2001Date of Patent: April 20, 2004Assignee: Intel CorporationInventors: Tim M. Gates, Brent S. Stone
-
Publication number: 20040061215Abstract: A fabrication method and semiconductor package provide enhanced performance. The semiconductor package includes a semiconductor die having an integrated circuit (IC), and a substrate having a die side coupled to the IC. A plurality of multi-signal bus bars is coupled to a socket side of the substrate such that the bus bars enable I/O signals to be transported between the substrate and a socket.Type: ApplicationFiled: September 26, 2003Publication date: April 1, 2004Inventors: Tim M. Gates, Brent S. Stone
-
Patent number: 6713684Abstract: A chip interface assembly and method of assembling a chip interface provide enhanced performance. The chip interface assembly includes a semiconductor package and a socket. The semiconductor package has a female contact architecture, where the female contact architecture is mated with a male contact architecture of the socket. By reversing the traditional male/female arrangement of conventional interconnection interfaces, difficulties associated with signaling throughput, clearance, hardware complexity and electrical losses can be obviated.Type: GrantFiled: November 1, 2001Date of Patent: March 30, 2004Assignee: Intel CorporationInventor: Brent S. Stone
-
Publication number: 20040056298Abstract: A chip interface assembly and method of assembling a chip interface provide enhanced performance. The chip interface assembly includes a semiconductor package and a socket. The semiconductor package has a female contact architecture, where the female contact architecture is mated with a male contact architecture of the socket. By reversing the traditional male/female arrangement of conventional interconnection interfaces, difficulties associated with signaling throughput, clearance, hardware complexity and electrical losses can be obviated.Type: ApplicationFiled: August 1, 2003Publication date: March 25, 2004Inventor: Brent S. Stone
-
Publication number: 20030089970Abstract: A fabrication method and semiconductor package provide enhanced performance. The semiconductor package includes a semiconductor die having an integrated circuit (IC), and a substrate having a die side coupled to the IC. A plurality of multi-signal bus bars is coupled to a socket side of the substrate such that the bus bars enable I/O signals to be transported between the substrate and a socket.Type: ApplicationFiled: November 9, 2001Publication date: May 15, 2003Inventors: Tim M. Gates, Brent S. Stone
-
Patent number: 6561820Abstract: A method and apparatus for a conductive plate for a socket. The conductive plate includes a plurality of openings. The conductive plate is electrically connected to ground and is contained within a socket that may receive an electronic package. The openings allow pins from the electronic package to pass through to contacts in the socket. The diameter of each opening is customizable to produce desired impedance between the electronic package pin inserted in the contact and the conductive plate. Impedance discontinuity seen by signals passing through the socket from the electronic package pins is reduced. The electronic plate may contain one or more pins insertable into contacts in the socket where the contacts provide the electrical connection to ground.Type: GrantFiled: September 27, 2001Date of Patent: May 13, 2003Assignee: Intel CorporationInventors: Brent S. Stone, Lesley A. Polka, Raj Nair, Sanjay Dabral
-
Publication number: 20030079908Abstract: A chip interface assembly and method of assembling a chip interface provide enhanced performance. The chip interface assembly includes a semiconductor package and a socket. The semiconductor package has a female contact architecture, where the female contact architecture is mated with a male contact architecture of the socket. By reversing the traditional male/female arrangement of conventional interconnection interfaces, difficulties associated with signaling throughput, clearance, hardware complexity and electrical losses can be obviated.Type: ApplicationFiled: November 1, 2001Publication date: May 1, 2003Inventor: Brent S. Stone
-
Publication number: 20030060063Abstract: A method and apparatus for a conductive plate for a socket. The conductive plate includes a plurality of openings. The conductive plate is electrically connected to ground and is contained within a socket that may receive an electronic package. The openings allow pins from the electronic package to pass through to contacts in the socket. The diameter of each opening is customizable to produce desired impedance between the electronic package pin inserted in the contact and the conductive plate. Impedance discontinuity seen by signals passing through the socket from the electronic package pins is reduced. The electronic plate may contain one or more pins insertable into contacts in the socket where the contacts provide the electrical connection to ground.Type: ApplicationFiled: September 27, 2001Publication date: March 27, 2003Inventors: Brent S. Stone, Lesley A. Polka, Raj Nair, Sanjay Dabral