Abstract: A phase-frequency detector (12) is configured for operating at a high frequency. A transition of a clock signal (REF CLK) is detected by a first latch (52) and a signal UP is generated. A transition of a feedback signal (FBK) is detected by a second latch (56) and a signal DOWN is generated. An logic circuit (64) detects the signals UP and the DOWN and generates a reset signal (RESET). A pulse-width of the reset signal (RESET) is controlled and limited by the logic circuit (64) to provide a faster response time for setting the first and second latches (52 and 56) to a state that allows detection of the phase and frequency differences between the clock signal (REF CLK) and the feedback signal (FBK).