Abstract: A method and apparatus for accessing a storage device is disclosed. More specifically, for load balancing by dynamically transferring memory address range assignments. In one embodiment, a storage device receives, from a host apparatus, an access request directed at two or more storage addresses, assigns, based on a first storage address of the two or more storage addresses, the access request to a first processor of two or more processors of the storage device, obtains a local memory lock based on the first storage address, determines, based on a second storage address of the two or more storage addresses, that the second storage address is assigned to a second processor of the two or more processors, obtains a remote memory lock from the second processor based on the second storage address and processes the access request.

Abstract: A method and apparatus for accessing a storage device is disclosed. More specifically, for load balancing by dynamically transferring memory address range assignments. In one embodiment, a storage device receives, from a host apparatus, an access request directed at two or more storage addresses, assigns, based on a first storage address of the two or more storage addresses, the access request to a first processor of two or more processors of the storage device, obtains a local memory lock based on the first storage address, determines, based on a second storage address of the two or more storage addresses, that the second storage address is assigned to a second processor of the two or more processors, obtains a remote memory lock from the second processor based on the second storage address and processes the access request.

Abstract: A method, a system and a computer program product for selecting a primary controller for a server system based on the services offered by each controller. A primary controller designator (PCD) utility determines the relative importance of a controller based upon the services provided by the controller and the weighted importance assigned to these services. The PCD utility classifies the services provided by a system-controller according to the following: (1) the number of OS partitions a system-controller is able to communicate with; and (2) the number of hardware devices that a controller has access to. The importance of the services is determined by the host OS partition information and the degree of importance of a partition that utilizes/requires the particular service(s). The PCD utility designates a controller as a “Primary” if the designated “Primary” is capable of providing services that are required for the most important OS partitions, according to the classification of controller services.

Abstract: A method, system, and computer usable program product for managing multi-node multi-version systems are provided in the illustrative embodiments. A process associates a version identifier with a first version of data available at a first node in the multi-node multi-version system. The version identifier corresponds to the first version of the data. The data includes an update. The process sends the data and the associated version identifier to a second node without learning a second version of data available at the second node. In one embodiment, the first version of data may be a subset of the second version of data. In another embodiment the second version of data may be a subset of the first version of data. The process repeats the sending for each update at the first node.

Abstract: A method, apparatus and computer program product are provided for implementing atomic data tracing in a processor system including an auxiliary processor unit (APU) coupled to a central processor unit (CPU). The auxiliary processor unit (APU) processes a trace instruction. When a trace instruction is identified by the APU, the APU signals the CPU with a pipeline stall signal for stalling the CPU and checks for an enabled trace engine as specified by the trace instruction. When the trace engine for the trace instruction is enabled, then the trace data is written into a trace buffer. The APU signals the CPU with an op done signal for allowing the CPU to continue with instruction processing.

Abstract: A method, a system and a computer program product for selecting a primary controller for a server system based on the services offered by each controller. A primary controller designator (PCD) utility determines the relative importance of a controller based upon the services provided by the controller and the weighted importance assigned to these services. The PCD utility classifies the services provided by a system-controller according to the following: (1) the number of OS partitions a system-controller is able to communicate with; and (2) the number of hardware devices that a controller has access to. The importance of the services is determined by the host OS partition information and the degree of importance of a partition that utilizes/requires the particular service(s). The PCD utility designates a controller as a “Primary” if the designated “Primary” is capable of providing services that are required for the most important OS partitions, according to the classification of controller services.

Abstract: In response to the start of an initialization sequence at a service processor, if power to a main processor was interrupted at a most-recent time that an operating system executed on the main processor, power to the main processor is turned on, the operating system is started executing on the main processor, data from the non-volatile memory of the service processor is provided to the operating system, and the service processor is reset, which restarts the initialization sequence. If the power to the main processor was not interrupted at the most-recent time that the operating system executed on the main processor, and if the operating system is currently executing on the main processor, a monitoring function is started in the service processor, which monitors for errors at a computer system.

Abstract: A method, system, and computer usable program product for managing multi-node multi-version systems are provided in the illustrative embodiments. A process associates a version identifier with a first version of data available at a first node in the multi-node multi-version system. The version identifier corresponds to the first version of the data. The data includes an update. The process sends the data and the associated version identifier to a second node without learning a second version of data available at the second node. In one embodiment, the first version of data may be a subset of the second version of data. In another embodiment the second version of data may be a subset of the first version of data. The process repeats the sending for each update at the first node.

Abstract: The aspects of the present invention provide a computer implemented method, an apparatus, and a computer usable program code for identifying a service processor with current setting information. First stored information for a service processor is retrieved from a first memory in the first service processor. Second stored information for the service processor is retrieved from a second memory in a data processing system to which the service processor is connected. The first stored information is compared with the second stored information to form a comparison as to whether the service processor was previously connected to the data processing system and to determine whether the service processor was a last service processor to fully communicate with system firmware in the data processing system. The service processor has current setting information if the service processor was previously connected to the data processing system and was the last service processor to fully communicate with the system firmware.

Abstract: A method, apparatus and computer program product are provided for implementing atomic data tracing in a processor system including an auxiliary processor unit (APU) coupled to a central processor unit (CPU). The auxiliary processor unit (APU) processes a trace instruction. When a trace instruction is identified by the APU, the APU signals the CPU with a pipeline stall signal for stalling the CPU and checks for an enabled trace engine as specified by the trace instruction. When the trace engine for the trace instruction is enabled, then the trace data is written into a trace buffer. The APU signals the CPU with an op done signal for allowing the CPU to continue with instruction processing.

Abstract: A method, apparatus and computer program product are provided for implementing atomic data tracing in a processor system including an auxiliary processor unit (APU) coupled to a central processor unit (CPU). The auxiliary processor unit (APU) processes a trace instruction. When a trace instruction is identified by the APU, the APU signals the CPU with a pipeline stall signal for stalling the CPU and checks for an enabled trace engine as specified by the trace instruction. When the trace engine for the trace instruction is enabled, then the trace data is written into a trace buffer. The APU signals the CPU with an op done signal for allowing the CPU to continue with instruction processing.

Abstract: In response to the start of an initialization sequence at a service processor, if power to a main processor was interrupted at a most-recent time that an operating system executed on the main processor, power to the main processor is turned on, the operating system is started executing on the main processor, data from the non-volatile memory of the service processor is provided to the operating system, and the service processor is reset, which restarts the initialization sequence. If the power to the main processor was not interrupted at the most-recent time that the operating system executed on the main processor, and if the operating system is currently executing on the main processor, a monitoring function is started in the service processor, which monitors for errors at a computer system.

Abstract: A method, computer program product, and a data processing system for generating a data dump in a data processing system is provided. A system boot of the data processing system is initialized. A firmware that includes fault collection logic is executed. A data dump is created in a persistent storage of the data processing system. An attempt is made to complete the system boot of the data processing system.

Abstract: A method, apparatus and computer program product are provided for implementing queue pair connection protection over an interconnect network, such as InfiniBand. A message packet is received for a queue pair (QP) and the QP is checked for an imminent connection failure. Responsive to identifying an imminent connection failure, a special message processing mode is established for the QP. After the special message processing mode is established, packets of the message are received without establishing a message queue entry and without storing packet data.

Abstract: A method and profiling cache for management of virtual memory includes a set of entries stored in the profiling cache. Each entry of the set of entries includes a page address, a time stamp for the page address and a least recently used (LRU) count; and the LRU count is updated for each access of the page address. Entries in the profiling cache are cast out using the LRU counts. A translation lookaside buffer (TLB) includes a first TLB section for storing a plurality of temporarily pinned entries and a second TLB section for storing a plurality of non-pinned entries. Responsive to a TLB interrupt, an entry is loaded in the second TLB section using a first in first out algorithm for replacing the non-pinned entries. The first TLB portion is periodically updated utilizing identified ones of the set of entries in the profiling cache having oldest time stamps.

Abstract: A method, apparatus and computer program product are provided for dynamically minimizing translation lookaside buffer (TLB) entries across contiguous memory. A page table with page table entries (PTEs) is provided for mapping multiple sized pages from a virtual address space to a physical address space. Each of the multiple sized pages is a multiple of a base page size. A region of memory having a starting address and a length is divided into a minimum number of natural blocks for the memory region. Once the region of memory is divided into the natural blocks, page table entries (PTEs) are assigned to map each natural block. Multiple identical PTEs are required to map each natural block greater than a base page size. Only one TLB entry is used to map each natural block.

Abstract: In a physical memory space, a pinned memory region is defined at one end of the space and a non-pinned region is defined at the other end of the space. A free region is between the pinned and non-pinned regions. Requests for pinned memory allocations are satisfied either by using holes in the pinned region or by appending the requested block to the end of the pinned region in the free region. The free region may be widened to accommodate pinned memory allocations. Requests for non-pinned memory allocations are satisfied by holes in the non-pinned region, by being appended to the non-pinned region in the free region or by filling holes in the pinned region, in that order.

Abstract: A method, apparatus and computer program product are provided for dynamically minimizing translation lookaside buffer (TLB) entries across contiguous memory. A page table with page table entries (PTEs) is provided for mapping multiple sized pages from a virtual address space to a physical address space. Each of the multiple sized pages is a multiple of a base page size. A region of memory having a starting address and a length is divided into a minimum number of natural blocks for the memory region. Once the region of memory is divided into the natural blocks, page table entries (PTEs) are assigned to map each natural block. Multiple identical PTEs are required to map each natural block greater than a base page size. Only one TLB entry is used to map each natural block.

Abstract: A method, apparatus and computer program product are provided for implementing queue pair connection protection over an interconnect network, such as InfiniBand. A message packet is received for a queue pair (QP) and the QP is checked for an imminent connection failure. Responsive to identifying an imminent connection failure, a special message processing mode is established for the QP. After the special message processing mode is established, packets of the message are received without establishing a message queue entry and without storing packet data.

Abstract: When a new control thread is initialized in a multi-thread software program, it is determined whether a like control thread has previously been instantiated. If so, a stack offset for the new control thread is set to be staggered from the stack offset for the previously instantiated like thread. By staggering the stack offsets of respective duplicate control threads, cache conflicts may be minimized.