Abstract: A current limited system for providing a burst current capability comprises a variable load having a first mode of operation requiring a first current level and a burst current mode of operation requiring a second current level. The second current level is greater than the first current level. A control processor provides control signals for the current limited system. A voltage source is connected to the variable load to provide a source current. The source current provides the variable load the first current level in the first mode of operation. A burst mode circuit provides the second current level to the variable load in the burst current mode of operation, responsive to the control signals from the control processor and the voltage source.

Abstract: A display management unit configured to provide a modified video signal for display on a target display over an electronic distribution network. The unit may access information regarding the target display and at least one input. The unit comprises a database interface configured to retrieve display characteristics corresponding to the information regarding the target display from a characteristics database, and a mapping unit configured to map at least one of tone and color values from the at least one input to corresponding mapped values based at least in part on the retrieved display characteristics to produce the modified video signal.

Abstract: An integrated control circuit is disclosed including a central processing unit operating in a normal full system power mode and in a reduced system low power mode, and a memory. A plurality of peripheral units are provided, at least one of which includes an input/output for interfacing with at least an external system for receiving information therefrom and a process block. The process block processes the received information from the external system and during the processing of the received information, data is stored in the at least one peripheral unit, and data is transferred at least to or at least from the memory. The input/output and process blocks are fully operable in the full system power mode and the reduced system power mode. A direct memory access (DMA) transfers data directly between the at least one peripheral and the memory when such data transfer is required by the peripheral.

Abstract: A system and method for enhancing data coherency and potential of at least one metadata associated with a video data configured to operate in a visual dynamic range (VDR) format is disclosed. The system comprises a metadata framing structure which includes a header start of frame bit set, a packet type bit set, a configuration bit set, a variable depth configuration/metadata bit set, a header end of frame bit set, a timestamp bit set for specifying a frame delay count to apply the at least one metadata to the video data and a checksum check bit set. The at least one metadata is designed to embed within a code word guard bit position of at least one color channel of the video data and adaptable to embed within the VDR pipeline to enhance the quality of the video data.

Abstract: A user interface is programmed to create a scorecard. The interface includes a scorecard module including a column area and a row area, and a key performance indicator area including a plurality of key performance indicators. A key performance indicator from the key performance indicator area can be dragged and dropped onto one of the column area and the row area to add indicia associated with the key performance indicator to the scorecard.

Abstract: A system includes a voltage regulator connected to a voltage source for providing a regulated voltage at a first level in a first mode of operation and at least one second level in a second mode of operation. The second voltage level is higher than the first voltage level. A control processor provides control signals to select between the first and the second modes of operation. A component associated with the voltage regulator. The component is disabled in the first mode of operation and enabled in the second mode of operation. The control processor generates control signals to configure the voltage regulator to generate the voltage at the first level in the first mode of operation when the component is disabled and to configure the voltage regulator to generate the voltage at the at least one second level in the second mode of operation when the component is enabled.

Abstract: A current limited system for providing a burst current capability comprises a variable load having a first mode of operation requiring a first current level and a burst current mode of operation requiring a second current level. The second current level is greater than the first current level. A control processor provides control signals for the current limited system. A voltage source is connected to the variable load to provide a source current. The source current provides the variable load the first current level in the first mode of operation. A burst mode circuit provides the second current level to the variable load in the burst current mode of operation, responsive to the control signals from the control processor and the voltage source.

Abstract: An integrated circuit comprises a host interface control block for providing a connection between the integrated circuit and a master controller device. The integrated circuit further includes a plurality of I/O pins. A capacitive touch sense circuitry enables detection of actuation of at least one capacitor switch of a capacitive sensor array connected to at least a portion of the plurality of I/O pins. An LCD controller drives at least one LCD connected to at least a portion of the plurality of I/O pins. The integrated circuit, responsive to signals received from the master controller device over the host interface control block, may be configured to monitor outputs from the capacitive sensor array in a first mode of operation. In a second mode of operation, the capacitive sensor array may be configured to drive at least one LCD. Finally, in a third mode of operation, the integrated circuit may be configured to both monitor outputs of the capacitive sensor array and drive the at least one LCD.

Abstract: A capacitive touch sensor circuitry comprises an interface for interconnecting with a plurality of I/O pins that connect to rows and columns of a capacitive sensor array. Monitoring circuitry, responsive to inputs from the plurality of I/O pins, determines when a capacitive switch in the capacitive sensor array has been actuated and stores an indication of the actuation of the capacitive switch. The monitoring circuitry then generates an interrupt responsive to the determined actuation. A control engine controls a manner in which the monitoring circuitry monitors the plurality of I/O pins. The control engine and the monitoring circuitry may be configured to monitor the plurality of I/O pins in a plurality of operating modes.

Abstract: Architecture for slicing data defined on both tabular data sources and in OLAP (online analytical processing) multidimensional data sources by time relative to the current date simultaneously with the same time intelligence (TI) filter on a dashboard page. The architecture employs a simple time period specification (STPS) language used to specify time periods in monitoring server TI filters, and key performance indicator (KPI) filters. The architecture maps all time dimensions to a common set of time aggregations (hierarchy) and to a common calendar.

Abstract: A user interface is programmed to create a scorecard. The interface includes a scorecard module including a column area and a row area, and a key performance indicator area including a plurality of key performance indicators. A key performance indicator from the key performance indicator area can be dragged and dropped onto one of the column area and the row area to add indicia associated with the key performance indicator to the scorecard.

Abstract: A laundry cart adapted for multiple configurations includes a body defining an end opening at a top of the body and a notch opening in a front wall. The body is adapted for alternative receipt of a lid covering the end opening or a removable extension vertically extending a cart interior. The depicted body includes a peripheral ledge and a raised lip at the top. The front wall includes a ledge and recessed surface for receiving a door covering the notch opening. The lid and door may engage each other to hold the door in a closed position. The cart may include attachment mechanisms for releasably attaching the removable extension to the body and door latches for holding the door in a closed position. The cart may include a hanger bar for suspending laundry in the interior.

Abstract: Hosted business service applications are provided enabling users to download and run plug-in modules associated with scorecard operations. Plug-in modules are launched from context-based links provided by the service or by third parties providing users the ability to work with the hosted application with a substantially same responsiveness and reliability as a natively installed application, to continue working while disconnected from the core service, and to have services upgraded without significantly disrupting their work. Client shell can be billed by the service or by third parties for the use of the business service by tracking activities associated with the downloaded module.

Abstract: Pen apparatus and method of assembly wherein a pick-up rod assembly performs in conjunction with a normally closed switch to define a pen-up tip switch condition. Coordinate signal information is provided from the pick-up rod assembly to a signal treatment network carried by an elongate printed circuit board which supplies a bias and electrical communication to the pick-up rod assembly through an electrically conductive helical spring. That spring also provides switch closure bias and tip switch information is transferred from the switch to a pen orientation detector network at the circuit board through a stamped metal transition component. Bias generated at the signal treatment network is further utilized in providing tip switch information to the pen orientation detector network.

Abstract: Method and apparatus for calibration of a low frequency oscillator in a processor based system. A method for calibrating an on-chip non-precision oscillator. An on-chip precision oscillator is provided having a known frequency of operation that is within an acceptable operating tolerance. The on-chip precision oscillator is used as a time base and then the period of the on-chip oscillator is measured as a function of the time base. The difference between the measured frequency of the on-chip non-precision oscillator and a desired operating frequency of the on-chip non-precision oscillator is then determined. After the difference is determined, the frequency of the on-chip non-precision oscillator is adjusted to minimize the determined difference.

Abstract: A system and method dynamically process video data received by a video decoder by determining a throttling amount, at a decoder throttling device, based on a measure of computational processing power required to decode at least one bitstream of the video data or the decoder's processing capabilities. The computational processing requirements of the decoder are controlled based on the throttling amount, including reducing the processing performed on the decoded video data prior to displaying a picture associated with the decoded video data. The decoder may reduce the amount of processing by limiting functions of at least one post filter or conversion filter. The computational processing requirements may also be controlled by comparing temporal references of two motion vectors of a picture of the video data, determining which motion vector has a closer temporal distance from the picture being decoded and processing only the motion vector having the closer temporal distance.

Abstract: A magnetic stripe card reader for reading a magnetic stripe on a card having at least one track of magnetically stored information stored thereon as a stream of encoded discrete data bits separated by bit times is disclosed. Aa magnetic head is provided for reading the magnetic pulses as the magnetic stripe is passed thereby to output a time varying analog signal. A data converter incorporated on an integrated circuit is then operable for converting the analog signal to a digital time series of digital values. A processor incorporated on the integrated circuit can ten process the digital output of the data converter and is operable to first determine potential bit boundaries and then recover timing information from the digital time series to discriminate the bit times between data bits. The value of each data bit is then determined during each bit time to provide a stream of extracted data bits.

Abstract: A circuit having an interconnect network and plurality of processing blocks is disclosed. The interconnect network has a plurality of network nodes arranged in a two-dimensional array on a first substrate. Each network node has a plurality of communication ports and is connected to each adjacent network node by a communication bus that connects only those two network nodes and processing blocks adjacent to that communication bus. A programmable switch within each node connects one of the input ports to one of the output ports in response to connection information stored in a memory in that node. Three-dimensional embodiments can be constructed by including a second substrate that overlies the first substrate and includes a second such interconnect network that is connected vertically through one or more nodes. The circuit easily accommodates spare processing blocks that can be substituted for defective blocks by altering the connection information.

Abstract: Method and apparatus for calibration of a low frequency oscillator in a processor based system. A method for calibrating an on-chip non-precision oscillator. An on-chip precision oscillator is provided having a known frequency of operation that is within an acceptable operating tolerance. The on-chip precision oscillator is used as a time base and then the period of the on-chip oscillator is measured as a function of the time base. The difference between the measured frequency of the on-chip non-precision oscillator and a desired operating frequency of the on-chip non-precision oscillator is then determined. After the difference is determined, the frequency of the on-chip non-precision oscillator is adjusted to minimize the determined difference.

Abstract: A magnetic stripe card reader for reading a magnetic stripe on a card having at least one track of magnetically stored information stored thereon as a stream of encoded discrete data bits separated by bit times is disclosed. Aa magnetic head is provided for reading the magnetic pulses as the magnetic stripe is passed thereby to output a time varying analog signal. A data converter incorporated on an integrated circuit is then operable for converting the analog signal to a digital time series of digital values. A processor incorporated on the integrated circuit can ten process the digital output of the data converter and is operable to first determine potential bit boundaries and then recover timing information from the digital time series to discriminate the bit times between data bits. The value of each data bit is then determined during each bit time to provide a stream of extracted data bits.