Patents by Inventor Bret Stott
Bret Stott has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11830573Abstract: A memory device includes a first receive circuit to receive a control signal of a memory access request from a memory controller. A second receive circuit receives a timing signal from the memory controller. The memory device includes circuitry to transmit, during a calibration mode of operation, feedback to the memory controller along a data path, the feedback indicative of a phase relationship been the control signal and the timing signal.Type: GrantFiled: March 25, 2022Date of Patent: November 28, 2023Assignee: Rambus Inc.Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
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Patent number: 11790962Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.Type: GrantFiled: July 12, 2021Date of Patent: October 17, 2023Assignee: RAMBUS INC.Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
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Publication number: 20220343956Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.Type: ApplicationFiled: March 25, 2022Publication date: October 27, 2022Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
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Patent number: 11302368Abstract: A memory device includes a first receive circuit to receive a control signal of a memory access request from a memory controller. A second receive circuit receives a timing signal from the memory controller. The memory device includes circuitry to transmit, during a calibration mode of operation, feedback to the memory controller along a data path, the feedback indicative of a phase relationship between the control signal and the timing signal.Type: GrantFiled: November 19, 2020Date of Patent: April 12, 2022Assignee: Rambus Inc.Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
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Publication number: 20220084571Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.Type: ApplicationFiled: July 12, 2021Publication date: March 17, 2022Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
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Patent number: 11062748Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.Type: GrantFiled: July 1, 2019Date of Patent: July 13, 2021Assignee: RAMBUS INC.Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
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Publication number: 20210193197Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.Type: ApplicationFiled: November 19, 2020Publication date: June 24, 2021Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
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Patent number: 10902891Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.Type: GrantFiled: February 28, 2020Date of Patent: January 26, 2021Assignee: Rambus Inc.Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
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Publication number: 20200294559Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.Type: ApplicationFiled: February 28, 2020Publication date: September 17, 2020Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
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Patent number: 10593379Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.Type: GrantFiled: August 22, 2018Date of Patent: March 17, 2020Assignee: Rambus Inc.Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
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Publication number: 20190392875Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.Type: ApplicationFiled: July 1, 2019Publication date: December 26, 2019Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
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Patent number: 10339990Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.Type: GrantFiled: July 31, 2017Date of Patent: July 2, 2019Assignee: RAMBUS INC.Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
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Publication number: 20190088295Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.Type: ApplicationFiled: August 22, 2018Publication date: March 21, 2019Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
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Patent number: 10062421Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.Type: GrantFiled: June 17, 2017Date of Patent: August 28, 2018Assignee: Rambus Inc.Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
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Publication number: 20180082725Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.Type: ApplicationFiled: July 31, 2017Publication date: March 22, 2018Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
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Publication number: 20170352390Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.Type: ApplicationFiled: June 17, 2017Publication date: December 7, 2017Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
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Patent number: 9721630Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.Type: GrantFiled: February 5, 2016Date of Patent: August 1, 2017Assignee: RAMBUS INC.Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
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Patent number: 9691447Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.Type: GrantFiled: September 23, 2015Date of Patent: June 27, 2017Assignee: Rambus Inc.Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
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Publication number: 20160232953Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.Type: ApplicationFiled: February 5, 2016Publication date: August 11, 2016Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
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Patent number: 9257163Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.Type: GrantFiled: August 5, 2013Date of Patent: February 9, 2016Assignee: RAMBUS INC.Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang