Patents by Inventor Brett Coon
Brett Coon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240004029Abstract: A method and a radar system are provided in the present disclosure. The radar system includes a radar unit having an antenna array configured to transmit and receive radar signal and a memory configured to store radar calibration parameters and radar channel parameters corresponding to the radar unit. The method provides for operation of the radar system. The radar system also includes a radar processor. The radar processor is configured to cause transmission of radar signals by the antenna array based on the radar channel parameters. The radar processor is also configured to process received radar signals based on the radar calibration parameters. The radar system further includes a central vehicle controller configured to operate a vehicle based on the processed radar signals.Type: ApplicationFiled: September 15, 2023Publication date: January 4, 2024Inventors: Kevin Duncklee, Brett Coon, Filip Perich
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Patent number: 11796633Abstract: A method and a radar system are provided in the present disclosure. The radar system includes a radar unit having an antenna array configured to transmit and receive radar signal and a memory configured to store radar calibration parameters and radar channel parameters corresponding to the radar unit. The method provides for operation of the radar system. The radar system also includes a radar processor. The radar processor is configured to cause transmission of radar signals by the antenna array based on the radar channel parameters. The radar processor is also configured to process received radar signals based on the radar calibration parameters. The radar system further includes a central vehicle controller configured to operate a vehicle based on the processed radar signals.Type: GrantFiled: December 16, 2019Date of Patent: October 24, 2023Assignee: Waymo LLCInventors: Kevin Duncklee, Brett Coon, Filip Perich
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Publication number: 20210181302Abstract: A method and a radar system are provided in the present disclosure. The radar system includes a radar unit having an antenna array configured to transmit and receive radar signal and a memory configured to store radar calibration parameters and radar channel parameters corresponding to the radar unit. The method provides for operation of the radar system. The radar system also includes a radar processor. The radar processor is configured to cause transmission of radar signals by the antenna array based on the radar channel parameters. The radar processor is also configured to process received radar signals based on the radar calibration parameters. The radar system further includes a central vehicle controller configured to operate a vehicle based on the processed radar signals.Type: ApplicationFiled: December 16, 2019Publication date: June 17, 2021Inventors: Kevin Duncklee, Brett Coon, Filip Perich
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Publication number: 20210080539Abstract: Examples relate to near-field radar filters that can enhance measurements near a radar unit. An example may involve receiving a first set of radar reflection signals at a radar unit coupled to a vehicle and determining a filter configured to offset near-field effects of radar reflection signals received at the radar unit. In some instances, the filter depends on an azimuth angle and a distance for surfaces in the environment causing the first set of radar reflection signals. The example may also involve receiving, at the radar unit, a second set of radar reflection signals and determining, using the filter, an azimuth angle and a distance for surfaces in the environment causing the second set of radar reflection signals. The vehicle may be controlled based in part on the azimuth angle and the distance for the surfaces causing the second plurality of radar reflection signals.Type: ApplicationFiled: November 19, 2020Publication date: March 18, 2021Inventors: Timothy Campbell, Brett Coon
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Patent number: 10866305Abstract: Examples relate to near-field radar filters that can enhance measurements near a radar unit. An example may involve receiving a first set of radar reflection signals at a radar unit coupled to a vehicle and determining a filter configured to offset near-field effects of radar reflection signals received at the radar unit. In some instances, the filter depends on an azimuth angle and a distance for surfaces in the environment causing the first set of radar reflection signals. The example may also involve receiving, at the radar unit, a second set of radar reflection signals and determining, using the filter, an azimuth angle and a distance for surfaces in the environment causing the second set of radar reflection signals. The vehicle may be controlled based in part on the azimuth angle and the distance for the surfaces causing the second plurality of radar reflection signals.Type: GrantFiled: May 8, 2018Date of Patent: December 15, 2020Assignee: Waymo LLCInventors: Timothy Campbell, Brett Coon
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Patent number: 8549266Abstract: A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern.Type: GrantFiled: June 7, 2011Date of Patent: October 1, 2013Inventors: John P. Banning, Eric Hao, Brett Coon
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Patent number: 8516224Abstract: Instructions asserted in the instruction pipeline of the microprocessor are accompanied by control information, comprising a group of bits, asserted within a control information pipeline of the processor. The control information pipeline is synchronized to the instruction pipeline so that the control information for an instruction progresses in synchronism with the instruction. The control information may identify, directly or indirectly, the type of operation called for by the instruction and, if the operation is to be performed in parts, indicate the part to be performed. Means are included in the processor, such as a number of functional execution units, to interpret that control information and take appropriate action.Type: GrantFiled: January 31, 2012Date of Patent: August 20, 2013Inventors: Brett Coon, Godfrey D'Souza, Paul Serris
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Publication number: 20120166768Abstract: Instructions asserted in the instruction pipeline of the microprocessor are accompanied by control information, comprising a group of bits, asserted within a control information pipeline of the processor. The control information pipeline is synchronized to the instruction pipeline so that the control information for an instruction progresses in synchronism with the instruction. The control information may identify, directly or indirectly, the type of operation called for by the instruction and, if the operation is to be performed in parts, indicate the part to be performed. Means are included in the processor, such as a number of functional execution units, to interpret that control information and take appropriate action.Type: ApplicationFiled: January 31, 2012Publication date: June 28, 2012Inventors: Brett Coon, Godfrey D'Souza, Paul Serris
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Patent number: 8117423Abstract: Instructions asserted in the instruction pipeline (3) of the microprocessor are accompanied by control information, comprising a group of bits, asserted within a control information pipeline (15) of the processor. The control information pipeline is synchronized to the instruction pipeline so that the control information for an instruction progresses in synchronism with the instruction. The control information may identify, directly or indirectly, the type of operation called for by the instruction and, if the operation is to be performed in parts, indicate the part to be performed. Means are included in the processor, such as a number of functional execution units (7), to interpret that control information and take appropriate action.Type: GrantFiled: March 4, 2008Date of Patent: February 14, 2012Inventors: Brett Coon, Godfrey D'Souza, Paul Serris
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Publication number: 20110238961Abstract: A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern.Type: ApplicationFiled: June 7, 2011Publication date: September 29, 2011Inventors: John Banning, Eric Hao, Brett Coon
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Patent number: 7984277Abstract: A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern.Type: GrantFiled: February 2, 2010Date of Patent: July 19, 2011Inventors: John Banning, Eric Hao, Brett Coon
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Patent number: 7886135Abstract: Instructions asserted in a microprocessors instruction pipeline (3) are accompanied by control information, comprising a group of bits, asserted within a control information pipeline (5) that is synchronized to the instruction pipeline. At the execution stage, the control information is interpreted and appropriate action taken. The control information may indicate that the instruction has been reasserted (asserted again following an initial assertion) and may also indicate the number of times that the instruction has been consecutively asserted in the instruction pipeline. Applied to unaligned memory operations, in which a memory atom is asserted twice, the control information indicates which part of the unaligned data is to be fetched each time the atom is executed.Type: GrantFiled: November 7, 2006Date of Patent: February 8, 2011Inventors: Brett Coon, Godfrey D'Souza, Paul Serris
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Publication number: 20100138638Abstract: A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern.Type: ApplicationFiled: February 2, 2010Publication date: June 3, 2010Inventors: John Banning, Eric Hao, Brett Coon
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Publication number: 20100122067Abstract: Instruction dispatch in a multithreaded microprocessor such as a graphics processor is not constrained by an order among the threads. Instructions for each thread are fetched, and a dispatch circuit determines which instructions in the buffer are ready to execute. The dispatch circuit may issue any ready instruction for execution, and an instruction from one thread may be issued prior to an instruction from another thread regardless of which instruction was fetched first. If multiple functional units are available, multiple instructions can be dispatched in parallel.Type: ApplicationFiled: January 20, 2010Publication date: May 13, 2010Applicant: NVIDIA CorporationInventors: John Erik Lindholm, Brett Coon, Simon S. Moy
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Patent number: 7698539Abstract: A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern.Type: GrantFiled: September 26, 2003Date of Patent: April 13, 2010Inventors: John P. Banning, Eric Hao, Brett Coon
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Patent number: 7685403Abstract: Instructions asserted in the instruction pipeline (3) of the microprocessor are accompanied by control information, comprising a group of bits, asserted within a control information pipeline (15) of the processor. The control information pipeline is synchronized to the instruction pipeline so that the control information for an instruction progresses in synchronism with the instruction. The control information may identify, directly or indirectly, the type of operation called for by the instruction and, if the operation is to be performed in parts, indicate the part to be performed. Means are included in to the processor, such as a number of functional execution units (7), to interpret that control information and take appropriate action.Type: GrantFiled: June 16, 2003Date of Patent: March 23, 2010Inventors: Brett Coon, Godfrey D'Souza, Paul Serris
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Patent number: 7676657Abstract: Instruction dispatch in a multithreaded microprocessor such as a graphics processor is not constrained by an order among the threads. Instructions for each thread are fetched, and a dispatch circuit determines which instructions in the buffer are ready to execute. The dispatch circuit may issue any ready instruction for execution, and an instruction from one thread may be issued prior to an instruction from another thread regardless of which instruction was fetched first. If multiple functional units are available, multiple instructions can be dispatched in parallel.Type: GrantFiled: October 10, 2006Date of Patent: March 9, 2010Assignee: NVIDIA CorporationInventors: John Erik Lindholm, Brett Coon, Simon S. Moy
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Patent number: 7664935Abstract: A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions.Type: GrantFiled: March 11, 2008Date of Patent: February 16, 2010Inventors: Brett Coon, Yoshiyuki Miyayama, Le Trong Nguyen, Johannes Wang
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Patent number: 7644210Abstract: Dynamic translation of indirect branch instructions of a target application by a host processor is enhanced by including a cache to provide access to the addresses of the most frequently used translations of a host computer, minimizing the need to access the translation buffer. Entries in the cache have a host instruction address and tags that may include a logical address of the instruction of the target application, the physical address of that instruction, the code segment limit to the instruction, and the context value of the host processor associated with that instruction. The cache may be a software cache apportioned by software from the main processor memory or a hardware cache separate from main memory.Type: GrantFiled: September 19, 2006Date of Patent: January 5, 2010Inventors: John Banning, Brett Coon, Linus Torvalds, Brian Choy, Malcolm Wing, Patrick Gainer
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Publication number: 20080162880Abstract: A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions.Type: ApplicationFiled: March 11, 2008Publication date: July 3, 2008Applicant: Transmeta CorporationInventors: Brett Coon, Yoshiyuki Miyayama, Le Trong Nguyen, Johannes Wang