Patents by Inventor Brett D. Grossman

Brett D. Grossman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit testing architecture
    Patent number: 9506980
    Abstract: In accordance with one aspect of the present description, an interface between an integrated circuit device and a test controller for testing the integrated circuit device includes a plurality of boards coupled together. In one embodiment, the test interface includes a plurality of interchangeable auxiliary boards, each having test circuitry, which may be coupled to a primary board and reused as appropriate to test various integrated circuits. Other aspects are described.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 29, 2016
    Assignee: INTEL CORPORATION
    Inventors: Abram M. Detofsky, Brett D. Grossman, Jin Pan, John M. Peterson, Ronald K. Minemier
  • Mechanism for facilitating an optical instrumentation testing system employing multiple testing paths
    Patent number: 9059803
    Abstract: A mechanism is described for facilitating optical testing of a device under test (DUT) using a testing mechanism having multiple testing paths according to one embodiment. A method of embodiments of the invention may include facilitating, via a loopback path, optical testing of the DUT in a loopback configuration. The loopback configuration may allow for looping between one or more transmitters and one or more receivers of the DUT. The method may further include facilitating, via a spectral path, spectral measurements relating to the DUT.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: June 16, 2015
    Assignee: Intel Corporation
    Inventors: Abram M. Detofsky, Chukwunenye S. Nnebe, Brett D. Grossman
  • INTEGRATED CIRCUIT TESTING ARCHITECTURE
    Publication number: 20140266285
    Abstract: In accordance with one aspect of the present description, an interface between an integrated circuit device and a test controller for testing the integrated circuit device includes a plurality of boards coupled together. In one embodiment, the test interface includes a plurality of interchangeable auxiliary boards, each having test circuitry, which may be coupled to a primary board and reused as appropriate to test various integrated circuits. Other aspects are described.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Abram M. DETOFSKY, Brett D. GROSSMAN, Jin PAN, John M. PETERSON, Ronald K. MINEMIER
  • MECHANISM FOR FACIILTATING AN OPTICAL INSTRUMENTATION TESTING SYSTEM EMPLOYING MULTIPLE TESTING PATHS
    Publication number: 20140092394
    Abstract: A mechanism is described for facilitating optical testing of a device under test (DUT) using a testing mechanism having multiple testing paths according to one embodiment. A method of embodiments of the invention may include facilitating, via a loopback path, optical testing of the DUT in a loopback configuration. The loopback configuration may allow for looping between one or more transmitters and one or more receivers of the DUT. The method may further include facilitating, via a spectral path, spectral measurements relating to the DUT.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: ABRAM M. DETOFSKY, Chukwunenye S. Nnebe, Brett D. Grossman